f2b4897773
The device has compatible flash macro with STM32F1 family, reuse stm32f1x driver code. Detect non-ARM target - for simplicy test target type name 'riscv' and the address has 32 bits. In case of RISC-V CPU use simple chunked write algo - async algo cannot be used as the core implemented in this device doesn't allow memory access while running. Change-Id: Ie3886fbd8573652691f91a02335812a7300689f7 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6704 Tested-by: jenkins Reviewed-by: Tim Newsome <tim@sifive.com> |
||
|---|---|---|
| .. | ||
| libdcc | ||
| loaders | ||
| remote_bitbang | ||
| rpc_examples | ||
| rtos-helpers | ||
| xsvf_tools | ||
| 60-openocd.rules | ||
| coresight-trace.txt | ||
| cross-build.sh | ||
| gen-stellaris-part-header.pl | ||
| itmdump.c | ||
| list_example.c | ||