619a4bbb7b
Change the GPIF state machine, configuring only one of the 4 waveforms to generate the clock signal (CCLK) used to program the FPGA, and send one byte every cycle using an 8-bit bus. Change-Id: I43cf5480b9d5c40cc2f6a62a52ecfe078b76458e Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7976 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins |
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.. | ||
buildroot | ||
firmware/angie | ||
libdcc | ||
loaders | ||
remote_bitbang | ||
rpc_examples | ||
rtos-helpers | ||
xsvf_tools | ||
60-openocd.rules | ||
coresight-trace.txt | ||
cross-build.sh | ||
gen-stellaris-part-header.pl | ||
itmdump.c | ||
list_example.c |