riscv-openocd

History

Tim Newsome e07613de33 Merge branch 'master' into from_upstream Conflicts: .gitmodules .travis.yml jimtcl src/jtag/core.c src/jtag/drivers/ftdi.c src/jtag/drivers/libjaylink src/jtag/drivers/mpsse.c src/jtag/drivers/stlink_usb.c src/rtos/hwthread.c src/target/riscv/riscv-013.c src/target/riscv/riscv.c tcl/board/sifive-hifive1-revb.cfg Change-Id: I2d26ebeffb4c1374730d2e20e6e2a7710403657c		2020-06-23 13:05:43 -07:00
..
checksum	Fix flashing HiFive Unleashed (#402 )	2019-09-09 12:01:17 -07:00
debug/xscale	coding style: contrib: remove empty lines at end of text files	2020-05-02 15:40:26 +01:00
erase_check	Merge branch 'master' into from_upstream	2020-06-23 13:05:43 -07:00
flash	Merge branch 'master' into from_upstream	2020-06-23 13:05:43 -07:00
watchdog	coding style: contrib: remove empty lines at end of text files	2020-05-02 15:40:26 +01:00
Makefile	From upstream (#331 )	2018-11-19 12:46:40 -08:00
README	cortex_m: target implementation renames cortex_m3 to cortex_m	2013-10-10 20:51:03 +00:00

README

Included in these directories are the src to the various ram loaders used
within openocd.

** target checksum loaders **

checksum/armv4_5_crc.s :
 - ARMv4 and ARMv5 checksum loader : see target/arm_crc_code.c:arm_crc_code

checksum/armv7m_crc.s :
 - ARMv7m checksum loader : see target/armv7m.c:cortex_m_crc_code

checksum/mips32.s :
 - MIPS32 checksum loader : see target/mips32.c:mips_crc_code

** target flash loaders **

flash/pic32mx.s :
 - Microchip PIC32 flash loader : see flash/nor/pic32mx.c:pic32mx_flash_write_code

flash/stellaris.s :
 - TI Stellaris flash loader : see flash/nor/stellaris.c:stellaris_write_code

flash/stm32x.s :
 - ST STM32 flash loader : see flash/nor/stm32x.c:stm32x_flash_write_code

flash/str7x.s :
 - ST STR7 flash loader : see flash/nor/str7x.c:str7x_flash_write_code

flash/str9x.s :
 - ST STR9 flash loader : see flash/nor/str9x.c:str9x_flash_write_code

Spencer Oliver
spen@spen-soft.co.uk