144 lines
3.4 KiB
INI
144 lines
3.4 KiB
INI
#
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# For each named Cortex-M3 vector_catch flag VECTOR ...
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# bus_err state_err
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# chk_err nocp_err
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# mm_err reset
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#
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# BUT NYET hard_err, int_err (their test cases don't yet work) ...
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#
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# Do the following:
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#
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# - Test #1: verify that OpenOCD ignores exceptions by default
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# + l_VECTOR (loads testcase to RAM)
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# + fault triggers loop-to-self exception "handler"
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# + "halt"
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# + observe fault "handling" -- loop-to-self from load_and_run (below)
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#
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# - Test #2: verify that "vector_catch" makes OpenOCD stops ignoring them
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# + cortex_m vector_catch none
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# + cortex_m vector_catch VECTOR
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# + l_VECTOR (loads testcase to RAM)
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# + fault triggers vector catch hardware
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# + observe OpenOCD entering debug state with no assistance
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#
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# NOTE "reset" includes the NVIC, so that test case gets its reset vector
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# from the flash, not from the vector table set up here. Which means that
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# for that vector_catch option, the Test #1 (above) "observe" step won't
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# use the SRAM address.
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#
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# we can fully automate test #2
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proc vector_test {tag} {
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halt
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# REVISIT -- annoying, we'd like to scrap vector_catch output
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cortex_m vector_catch none
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cortex_m vector_catch $tag
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eval "l_$tag"
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}
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#
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# Load and start one vector_catch test case.
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#
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# name -- tag for the vector_catch flag being tested
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# halfwords -- array of instructions (some wide, some narrow)
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# n_instr -- how many instructions are in $halfwords
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#
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proc load_and_run { name halfwords n_instr } {
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reset halt
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# Load code at beginning of SRAM.
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echo "# code to trigger $name vector"
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set addr 0x20000000
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# array2mem should be faster, though we'd need to
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# compute the resulting $addr ourselves
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foreach opcode $halfwords {
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mwh $addr $opcode
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incr addr 2
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}
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# create default loop-to-self at $addr ... it serves as
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# (a) "main loop" on error
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# (b) handler for all exceptions that get triggered
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mwh $addr 0xe7fe
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# disassemble, as sanity check and what's-happening trace
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arm disassemble 0x20000000 [expr 1 + $n_instr ]
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# Assume that block of code is at most 16 halfwords long.
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# Create a basic table of loop-to-self exception handlers.
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mww 0x20000020 $addr 16
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# Store its address in VTOR
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mww 0xe000ed08 0x20000020
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# Use SHCSR to ensure nothing escalates to a HardFault
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mww 0xe000ed24 0x00070000
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# now start, trigering the $name vector catch logic
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resume 0x20000000
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}
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#proc l_hard_err {} {
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# IMPLEMENT ME
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# FORCED -- escalate something to HardFault
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#}
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#proc l_int_err {} {
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# IMPLEMENT ME
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# STKERR -- exception stack BusFault
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#}
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# BusFault, escalates to HardFault
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proc l_bus_err {} {
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# PRECISERR -- assume less than 512 MBytes of SRAM
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load_and_run bus_err {
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0xf06f 0x4040
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0x7800
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} 2
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}
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# UsageFault, escalates to HardFault
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proc l_state_err {} {
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# UNDEFINSTR -- issue architecturally undefined instruction
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load_and_run state_err {
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0xde00
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} 1
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}
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# UsageFault, escalates to HardFault
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proc l_chk_err {} {
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# UNALIGNED -- LDM through unaligned pointer
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load_and_run chk_err {
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0xf04f 0x0001
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0xe890 0x0006
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} 2
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}
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# UsageFault, escalates to HardFault
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proc l_nocp_err {} {
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# NOCP -- issue cp14 DCC instruction
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load_and_run nocp_err {
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0xee10 0x0e15
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} 1
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}
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# MemManage, escalates to HardFault
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proc l_mm_err {} {
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# IACCVIOL -- instruction fetch from an XN region
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load_and_run mm_err {
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0xf04f 0x4060
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0x4687
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} 2
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}
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proc l_reset {} {
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# issue SYSRESETREQ via AIRCR
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load_and_run reset {
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0xf04f 0x0104
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0xf2c0 0x51fa
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0xf44f 0x406d
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0xf100 0x000c
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0xf2ce 0x0000
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0x6001
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} 6
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}
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