307 lines
5.6 KiB
ArmAsm
307 lines
5.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* SH QSPI (Quad SPI) driver
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* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
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*/
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#define BIT(n) (1UL << (n))
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/* SH QSPI register bit masks <REG>_<BIT> */
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#define SPCR_MSTR 0x08
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#define SPCR_SPE 0x40
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#define SPSR_SPRFF 0x80
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#define SPSR_SPTEF 0x20
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#define SPPCR_IO3FV 0x04
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#define SPPCR_IO2FV 0x02
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#define SPPCR_IO1FV 0x01
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#define SPBDCR_RXBC0 BIT(0)
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#define SPCMD_SCKDEN BIT(15)
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#define SPCMD_SLNDEN BIT(14)
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#define SPCMD_SPNDEN BIT(13)
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#define SPCMD_SSLKP BIT(7)
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#define SPCMD_BRDV0 BIT(2)
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#define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
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SPCMD_SPNDEN | SPCMD_SSLKP | \
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SPCMD_BRDV0
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#define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
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SPCMD_BRDV0
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#define SPBFCR_TXRST BIT(7)
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#define SPBFCR_RXRST BIT(6)
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#define SPBFCR_TXTRG 0x30
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#define SPBFCR_RXTRG 0x07
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/* SH QSPI register set */
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#define SH_QSPI_SPCR 0x00
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#define SH_QSPI_SSLP 0x01
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#define SH_QSPI_SPPCR 0x02
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#define SH_QSPI_SPSR 0x03
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#define SH_QSPI_SPDR 0x04
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#define SH_QSPI_SPSCR 0x08
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#define SH_QSPI_SPSSR 0x09
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#define SH_QSPI_SPBR 0x0a
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#define SH_QSPI_SPDCR 0x0b
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#define SH_QSPI_SPCKD 0x0c
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#define SH_QSPI_SSLND 0x0d
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#define SH_QSPI_SPND 0x0e
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#define SH_QSPI_DUMMY0 0x0f
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#define SH_QSPI_SPCMD0 0x10
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#define SH_QSPI_SPCMD1 0x12
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#define SH_QSPI_SPCMD2 0x14
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#define SH_QSPI_SPCMD3 0x16
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#define SH_QSPI_SPBFCR 0x18
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#define SH_QSPI_DUMMY1 0x19
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#define SH_QSPI_SPBDCR 0x1a
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#define SH_QSPI_SPBMUL0 0x1c
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#define SH_QSPI_SPBMUL1 0x20
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#define SH_QSPI_SPBMUL2 0x24
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#define SH_QSPI_SPBMUL3 0x28
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.syntax unified
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.arm
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.text
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.macro wait_for_spsr, spsrbit
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1: ldrb r12, [r0, #SH_QSPI_SPSR]
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tst r12, \spsrbit
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beq 1b
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.endm
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.macro sh_qspi_xfer
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bl sh_qspi_cs_activate
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str r6, [r0, SH_QSPI_SPBMUL0]
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bl sh_qspi_xfer_common
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bl sh_qspi_cs_deactivate
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.endm
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.macro sh_qspi_write_enable
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ldr r4, =SPIFLASH_WRITE_ENABLE
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adr r5, _start
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add r4, r5
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mov r5, #0x0
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mov r6, #0x1
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sh_qspi_xfer
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.endm
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.macro sh_qspi_wait_till_ready
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1: ldr r4, =SPIFLASH_READ_STATUS
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adr r5, _start
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add r4, r5
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mov r5, #0x0
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mov r6, #0x2
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sh_qspi_xfer
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and r13, #0x1
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cmp r13, #0x1
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beq 1b
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.endm
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/*
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* r0: controller base address
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* r1: data buffer base address
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* r2: BIT(31) -- page program (not read)
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* BIT(30) -- 4-byte address (not 3-byte)
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* BIT(29) -- 512-byte page (not 256-byte)
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* BIT(27:20) -- SF command
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* BIT(19:0) -- amount of data to read/write
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* r3: SF target address
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*
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* r7: data size
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* r8: page size
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*
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* r14: lr, link register
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* r15: pc, program counter
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*
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* Clobber: r4, r5, r6, r7, r8
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*/
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.global _start
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_start:
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bic r7, r2, #0xff000000
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bic r7, r7, #0x00f00000
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and r8, r2, #(1 << 31)
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cmp r8, #(1 << 31)
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beq do_page_program
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/* fast read */
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bl sh_qspi_cs_activate
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bl sh_qspi_setup_command
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add r8, r6, r7
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str r8, [r0, SH_QSPI_SPBMUL0]
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bl sh_qspi_xfer_common
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mov r4, #0x0
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mov r5, r1
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mov r6, r7
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bl sh_qspi_xfer_common
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bl sh_qspi_cs_deactivate
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b end
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do_page_program:
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mov r8, #0x100
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tst r2, (1 << 29)
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movne r8, #0x200
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do_pp_next_page:
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/* Check if less then page bytes left. */
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cmp r7, r8
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movlt r8, r7
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sh_qspi_write_enable
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bl sh_qspi_cs_activate
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bl sh_qspi_setup_command
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str r6, [r0, SH_QSPI_SPBMUL0]
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bl sh_qspi_xfer_common
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mov r4, r1
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mov r5, #0x0
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mov r6, r8
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bl sh_qspi_xfer_common
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bl sh_qspi_cs_deactivate
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sh_qspi_wait_till_ready
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add r1, r8
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add r3, r8
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sub r7, r8
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cmp r7, #0
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bne do_pp_next_page
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end:
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bkpt #0
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sh_qspi_cs_activate:
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/* Set master mode only */
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mov r12, #SPCR_MSTR
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strb r12, [r0, SH_QSPI_SPCR]
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/* Set command */
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mov r12, #SPCMD_INIT1
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strh r12, [r0, SH_QSPI_SPCMD0]
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/* Reset transfer and receive Buffer */
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ldrb r12, [r0, SH_QSPI_SPSCR]
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orr r12, #(SPBFCR_TXRST | SPBFCR_RXRST)
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strb r12, [r0, SH_QSPI_SPBFCR]
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/* Clear transfer and receive Buffer control bit */
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ldrb r12, [r0, SH_QSPI_SPBFCR]
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bic r12, #(SPBFCR_TXRST | SPBFCR_RXRST)
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strb r12, [r0, SH_QSPI_SPBFCR]
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/* Set sequence control method. Use sequence0 only */
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mov r12, #0x00
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strb r12, [r0, SH_QSPI_SPSCR]
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/* Enable SPI function */
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ldrb r12, [r0, SH_QSPI_SPCR]
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orr r12, #SPCR_SPE
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strb r12, [r0, SH_QSPI_SPCR]
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mov pc, lr
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sh_qspi_cs_deactivate:
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/* Disable SPI function */
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ldrb r12, [r0, SH_QSPI_SPCR]
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bic r12, #SPCR_SPE
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strb r12, [r0, SH_QSPI_SPCR]
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mov pc, lr
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/*
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* r0, controller base address
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* r4, tx buffer
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* r5, rx buffer
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* r6, xfer len, non-zero
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*
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* Upon exit, r13 contains the last byte in SPDR
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*
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* Clobber: r11, r12, r13
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*/
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sh_qspi_xfer_common:
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prepcopy:
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ldr r13, [r0, #SH_QSPI_SPBFCR]
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orr r13, #(SPBFCR_TXTRG | SPBFCR_RXTRG)
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mov r11, #32
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cmp r6, #32
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biclt r13, #(SPBFCR_TXTRG | SPBFCR_RXTRG)
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movlt r11, #1
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copy:
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str r13, [r0, #SH_QSPI_SPBFCR]
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wait_for_spsr SPSR_SPTEF
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mov r12, r11
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mov r13, #0
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cmp r4, #0
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beq 3f
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2: ldrb r13, [r4], #1
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strb r13, [r0, #SH_QSPI_SPDR]
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subs r12, #1
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bne 2b
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b 4f
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3: strb r13, [r0, #SH_QSPI_SPDR]
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subs r12, #1
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bne 3b
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4: wait_for_spsr SPSR_SPRFF
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mov r12, r11
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cmp r5, #0
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beq 6f
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5: ldrb r13, [r0, #SH_QSPI_SPDR]
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strb r13, [r5], #1
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subs r12, #1
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bne 5b
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b 7f
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6: ldrb r13, [r0, #SH_QSPI_SPDR]
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subs r12, #1
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bne 6b
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7: subs r6, r11
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bne prepcopy
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mov pc, lr
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sh_qspi_setup_command:
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ldr r4, =SPIFLASH_SCRATCH_DATA
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adr r5, _start
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add r4, r5
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and r12, r2, #0x0ff00000
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lsr r12, #20
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strb r12, [r4]
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mov r12, r3
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strb r12, [r4, #4]
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lsr r12, #8
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strb r12, [r4, #3]
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lsr r12, #8
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strb r12, [r4, #2]
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lsr r12, #8
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strb r12, [r4, #1]
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lsr r12, #8
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mov r5, #0x0
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mov r6, #0x4
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tst r2, (1 << 30)
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movne r6, #0x5
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mov pc, lr
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SPIFLASH_READ_STATUS: .byte 0x05 /* Read Status Register */
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SPIFLASH_WRITE_ENABLE: .byte 0x06 /* Write Enable */
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SPIFLASH_NOOP: .byte 0x00
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SPIFLASH_SCRATCH_DATA: .byte 0x00, 0x0, 0x0, 0x0, 0x0
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