153 lines
3.8 KiB
C
153 lines
3.8 KiB
C
/*
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* COMPILE: arm-none-eabi-gcc -mthumb -march=armv7-m ...
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* ... plus, provide at least a default exception vector table.
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*
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* RUN: this is best run from SRAM. It starts at main() then triggers
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* a fault before more than a handful of instructions have executed.
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* Run each test case in two modes:
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*
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* (1) Faults caught on the Cortex-M3. Default handlers are usually
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* loop-to-self NOPs, so a debugger won't notice faults until they
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* halt the core and examine xSPR and other registers.
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*
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* To verify the fault triggered, issue "halt" from OpenOCD; you
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* should be told about the fault and (some of) its details.
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* Then it's time to run the next test.
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*
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* NOTE however that "reset" will restart everything; verify that
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* case by observing your reset handler doing its normal work.
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*
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* (2) Faults intercepted by OpenOCD "vector_catch ..." commands.
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*
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* OpenOCD should tell you about the fault, and show the same
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* details, without your "halt" command.
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*
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* Someday, a fancy version of this code could provide a vector table and
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* fault handlers which use semihosting (when that works on Cortex-M3) to
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* report what happened, again without needing a "halt" command.
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*/
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/* These symbols match the OpenOCD "cortex_m vector_catch" bit names. */
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enum vc_case {
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hard_err,
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int_err,
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bus_err,
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state_err,
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chk_err,
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nocp_err,
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mm_err,
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reset,
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};
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/* REVISIT come up with a way to avoid recompiling, maybe:
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* - write it in RAM before starting
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* - compiled-in BKPT, manual patch of r0, then resume
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* - ...
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*/
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#ifndef VC_ID
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#warning "no VC_ID ... using reset"
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#define VC_ID reset
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#endif
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int main(void) __attribute__ ((externally_visible, noreturn));
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/*
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* Trigger various Cortex-M3 faults to verify that OpenOCD behaves OK
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* in terms of its vector_catch handling.
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*
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* Fault handling should be left entirely up to the application code
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* UNLESS a "vector_catch" command tells OpenOCD to intercept a fault.
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*
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* See ARMv7-M architecure spec table B1-9 for the list of faults and
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* their mappings to the vector catch bits.
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*/
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int main(void)
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{
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/* One test case for each vector catch bit. We're not doing
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* hardware testing; so it doesn't matter when some DEMCR bits
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* could apply in multiple ways.
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*/
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switch (VC_ID) {
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/* "cortex_m vector_catch hard_err" */
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case hard_err:
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/* FORCED - Fault escalation */
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/* FIXME code this */
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break;
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/* "cortex_m vector_catch int_err" */
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case int_err:
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/* STKERR -- Exception stack BusFault */
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/* FIXME code this */
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break;
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/* "cortex_m vector_catch bus_err" */
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case bus_err:
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/* PRECISERR -- precise data bus read
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* Here we assume a Cortex-M3 with 512 MBytes SRAM is very
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* unlikely, so the last SRAM byte isn't a valid address.
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*/
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__asm__ volatile(
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"mov r0, #0x3fffffff\n"
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"ldrb r0, [r0]\n"
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);
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break;
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/* "cortex_m vector_catch state_err" */
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case state_err:
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/* UNDEFINSTR -- architectural undefined instruction */
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__asm__ volatile(".hword 0xde00");
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break;
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/* "cortex_m vector_catch chk_err" */
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case chk_err:
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/* UNALIGNED ldm */
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__asm__ volatile(
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"mov r0, #1\n"
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"ldm r0, {r1, r2}\n"
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);
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break;
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/* "cortex_m vector_catch nocp_err" */
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case nocp_err:
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/* NOCP ... Cortex-M3 has no coprocessors (like CP14 DCC),
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* but these instructions are allowed by ARMv7-M.
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*/
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__asm__ volatile("mrc p14, 0, r0, c0, c5, 0");
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break;
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/* "cortex_m vector_catch mm_err" */
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case mm_err:
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/* IACCVIOL -- instruction fetch from an XN region */
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__asm__ volatile(
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"mov r0, #0xe0000000\n"
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"mov pc, r0\n"
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);
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break;
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/* "cortex_m vector_catch reset" */
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case reset:
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__asm__ volatile(
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/* r1 = SYSRESETREQ */
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"mov r1, #0x0004\n"
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/* r1 |= VECTKEY */
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"movt r1, #0x05fa\n"
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/* r0 = &AIRCR */
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"mov r0, #0xed00\n"
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"add r0, #0xc\n"
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"movt r0, #0xe000\n"
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/* AIRCR = ... */
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"str r1, [r0, #0]\n"
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);
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break;
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}
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/* don't return */
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while (1)
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continue;
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}
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