326 lines
4.2 KiB
C
326 lines
4.2 KiB
C
/***************************************************************************
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* Copyright (C) 2013 Andes Technology *
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* Hsiangkai Wang <hkwang@andestech.com> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_NDS32_REG_H
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#define OPENOCD_TARGET_NDS32_REG_H
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#define SRIDX(a, b, c) ((a << 7) | (b << 3) | c)
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#define NDS32_REGISTER_DISABLE (0x0)
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enum nds32_reg_number_s {
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R0 = 0, /* general registers */
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R1,
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R2,
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R3,
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R4,
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R5,
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R6,
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R7,
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R8,
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R9,
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R10,
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R11,
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R12,
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R13,
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R14,
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R15,
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R16,
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R17,
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R18,
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R19,
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R20,
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R21,
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R22,
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R23,
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R24,
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R25,
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R26,
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R27,
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R28,
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R29,
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R30,
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R31,
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PC,
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D0LO,
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D0HI,
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D1LO,
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D1HI,
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ITB,
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IFC_LP,
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CR0, /* system registers */
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CR1,
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CR2,
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CR3,
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CR4,
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CR5,
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CR6,
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IR0,
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IR1,
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IR2,
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IR3,
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IR4,
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IR5,
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IR6,
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IR7,
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IR8,
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IR9,
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IR10,
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IR11,
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IR12,
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IR13,
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IR14,
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IR15,
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IR16,
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IR17,
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IR18,
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IR19,
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IR20,
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IR21,
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IR22,
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IR23,
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IR24,
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IR25,
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IR26,
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IR27,
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IR28,
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IR29,
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IR30,
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MR0,
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MR1,
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MR2,
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MR3,
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MR4,
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MR5,
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MR6,
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MR7,
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MR8,
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MR9,
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MR10,
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MR11,
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DR0,
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DR1,
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DR2,
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DR3,
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DR4,
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DR5,
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DR6,
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DR7,
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DR8,
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DR9,
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DR10,
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DR11,
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DR12,
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DR13,
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DR14,
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DR15,
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DR16,
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DR17,
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DR18,
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DR19,
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DR20,
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DR21,
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DR22,
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DR23,
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DR24,
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DR25,
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DR26,
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DR27,
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DR28,
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DR29,
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DR30,
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DR31,
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DR32,
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DR33,
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DR34,
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DR35,
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DR36,
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DR37,
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DR38,
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DR39,
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DR40,
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DR41,
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DR42,
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DR43,
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DR44,
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DR45,
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DR46,
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DR47,
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DR48,
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PFR0,
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PFR1,
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PFR2,
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PFR3,
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DMAR0,
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DMAR1,
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DMAR2,
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DMAR3,
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DMAR4,
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DMAR5,
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DMAR6,
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DMAR7,
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DMAR8,
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DMAR9,
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DMAR10,
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RACR,
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FUCPR,
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IDR0,
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IDR1,
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SECUR0,
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D0L24, /* audio registers */
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D1L24,
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I0,
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I1,
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I2,
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I3,
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I4,
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I5,
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I6,
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I7,
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M1,
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M2,
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M3,
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M5,
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M6,
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M7,
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MOD,
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LBE,
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LE,
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LC,
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ADM_VBASE,
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SHFT_CTL0,
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SHFT_CTL1,
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CB_CTL,
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CBB0,
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CBB1,
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CBB2,
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CBB3,
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CBE0,
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CBE1,
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CBE2,
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CBE3,
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FPCSR, /* fpu */
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FPCFG,
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FS0,
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FS1,
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FS2,
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FS3,
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FS4,
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FS5,
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FS6,
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FS7,
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FS8,
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FS9,
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FS10,
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FS11,
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FS12,
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FS13,
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FS14,
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FS15,
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FS16,
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FS17,
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FS18,
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FS19,
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FS20,
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FS21,
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FS22,
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FS23,
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FS24,
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FS25,
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FS26,
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FS27,
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FS28,
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FS29,
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FS30,
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FS31,
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FD0,
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FD1,
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FD2,
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FD3,
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FD4,
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FD5,
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FD6,
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FD7,
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FD8,
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FD9,
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FD10,
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FD11,
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FD12,
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FD13,
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FD14,
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FD15,
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FD16,
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FD17,
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FD18,
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FD19,
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FD20,
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FD21,
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FD22,
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FD23,
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FD24,
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FD25,
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FD26,
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FD27,
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FD28,
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FD29,
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FD30,
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FD31,
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TOTAL_REG_NUM,
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};
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enum nds32_reg_type_s {
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NDS32_REG_TYPE_GPR = 0,
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NDS32_REG_TYPE_SPR,
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NDS32_REG_TYPE_CR,
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NDS32_REG_TYPE_IR,
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NDS32_REG_TYPE_MR,
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NDS32_REG_TYPE_DR,
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NDS32_REG_TYPE_PFR,
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NDS32_REG_TYPE_DMAR,
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NDS32_REG_TYPE_RACR,
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NDS32_REG_TYPE_IDR,
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NDS32_REG_TYPE_AUMR,
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NDS32_REG_TYPE_SECURE,
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NDS32_REG_TYPE_FPU,
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};
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struct nds32_reg_s {
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const char *simple_mnemonic;
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const char *symbolic_mnemonic;
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uint32_t sr_index;
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enum nds32_reg_type_s type;
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uint8_t size;
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};
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struct nds32_reg_exception_s {
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uint32_t reg_num;
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uint32_t ex_value_bit_pos;
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uint32_t ex_value_mask;
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uint32_t ex_value;
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};
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void nds32_reg_init(void);
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uint32_t nds32_reg_sr_index(uint32_t number);
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enum nds32_reg_type_s nds32_reg_type(uint32_t number);
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uint8_t nds32_reg_size(uint32_t number);
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const char *nds32_reg_simple_name(uint32_t number);
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const char *nds32_reg_symbolic_name(uint32_t number);
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bool nds32_reg_exception(uint32_t number, uint32_t value);
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#endif /* OPENOCD_TARGET_NDS32_REG_H */
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