97 lines
1.9 KiB
VHDL
97 lines
1.9 KiB
VHDL
-- SPDX-License-Identifier: BSD-3-Clause
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----------------------------------------------------------------------------
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-- Project Context: nanoXplore USB-JTAG Adapter Board, Spartan6
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-- Design Name: NJTAG USB-JTAG Adapter FPGA source code
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-- Module Name: _angie_openocd.vhd
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-- Target Device: XC6SLX9-2 TQ144
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-- Tool versions: ISE Webpack 13.2 -> 14.2
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-- Author: Ahmed BOUDJELIDA nanoXplore SAS
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----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library UNISIM;
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use UNISIM.VComponents.all;
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entity S609 is port(
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TRST : in std_logic;
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TMS : in std_logic;
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TCK : in std_logic;
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TDI : in std_logic;
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TDO : out std_logic;
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SRST : in std_logic;
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SDA : inout std_logic;
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SDA_DIR : in std_logic;
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SCL : in std_logic;
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FTP : out std_logic_vector(7 downto 0):=(others => '1'); -- Test points
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SI_TDO : in std_logic;
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ST_0 : out std_logic;
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ST_1 : out std_logic;
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ST_2 : out std_logic;
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ST_4 : out std_logic;
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ST_5 : out std_logic;
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SO_SDA_OUT : out std_logic;
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SO_SDA_IN : in std_logic;
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SO_SCL : out std_logic;
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SO_TRST : out std_logic;
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SO_TMS : out std_logic;
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SO_TCK : out std_logic;
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SO_TDI : out std_logic;
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SO_SRST : out std_logic
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);
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end S609;
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architecture A_S609 of S609 is
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begin
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--Directions:
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ST_0 <= '0';
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ST_1 <= '1';
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ST_4 <= '0';
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--TDO:
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TDO <= not SI_TDO;
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--TRST - TCK - TMS - TDI:
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SO_TRST <= TRST;
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SO_TMS <= TMS;
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SO_TCK <= TCK;
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SO_TDI <= TDI;
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ST_2 <= SRST;
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SO_SRST <= '0';
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SO_SCL <= SCL;
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SDA <= not(SO_SDA_IN) when (SDA_DIR = '1') else 'Z';
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SO_SDA_OUT <= SDA;
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process(SDA_DIR)
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begin
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if(SDA_DIR = '1') then
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ST_5 <= '1';
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else
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ST_5 <= '0';
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end if;
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end process;
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--Points de test:
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FTP(0) <= SDA;
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FTP(1) <= SCL;
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FTP(2) <= not(SO_SDA_IN);
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FTP(3) <= SDA_DIR;
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FTP(5) <= SRST;
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FTP(4) <= SI_TDO;
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FTP(6) <= '1';
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FTP(7) <= '1';
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end A_S609;
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