Tim Newsome c5dee66a71 Redo fespi flash algorithm (#384) ... * WIP, rewrite of flash algorithm. Just put all the flashing logic into the algorithm, instead of using an intermediate format. This should reduce total data written while flashing by about 9%, and also makes the code much simpler. Change-Id: I807e60c8ab4f9f376cceaecdbbd10a2326be1c79 * New algorithm works. Speeds up Arty flashing another 9%. wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 86.784538s (25.074 KiB/s) verified 2192012 bytes in 6.693336s (319.816 KiB/s) 8.66user 13.03system 1:33.91elapsed 23%CPU (0avgtext+0avgdata 12272maxresident)k Change-Id: Ie55c5250d667251be141cb32b144bbcf3713fce4 * Fix whitespace. Change-Id: I338d518fa11a108efb530ffe75a2030619457a0b * Don't reserve so much stack space. Also properly check XLEN in riscv_wrapper.S. Change-Id: Ifa0301f3ea80f648fb8a6d6b6c8bf39f386fe4a6		2019-07-09 10:05:07 -07:00
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Makefile	Redo fespi flash algorithm (#384)	2019-07-09 10:05:07 -07:00
fespi.S	Add flash support for SiFive's Freedom E platforms	2019-01-11 19:50:09 +00:00
riscv.lds	Redo fespi flash algorithm (#384)	2019-07-09 10:05:07 -07:00
riscv32_fespi.inc	Redo fespi flash algorithm (#384)	2019-07-09 10:05:07 -07:00
riscv64_fespi.inc	Redo fespi flash algorithm (#384)	2019-07-09 10:05:07 -07:00
riscv_fespi.c	Redo fespi flash algorithm (#384)	2019-07-09 10:05:07 -07:00
riscv_wrapper.S	Redo fespi flash algorithm (#384)	2019-07-09 10:05:07 -07:00