96 lines
4.4 KiB
Tcl
96 lines
4.4 KiB
Tcl
# /* Peripheral and SRAM base address in the alias region */
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set PERIPH_BB_BASE 0x42000000
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set SRAM_BB_BASE 0x22000000
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# /*Peripheral and SRAM base address in the bit-band region */
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set SRAM_BASE 0x20000000
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set PERIPH_BASE 0x40000000
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# /*FSMC registers base address */
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set FSMC_R_BASE 0xA0000000
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# /*Peripheral memory map */
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set APB1PERIPH_BASE [set PERIPH_BASE]
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set APB2PERIPH_BASE [expr $PERIPH_BASE + 0x10000]
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set AHBPERIPH_BASE [expr $PERIPH_BASE + 0x20000]
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set TIM2_BASE [expr $APB1PERIPH_BASE + 0x0000]
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set TIM3_BASE [expr $APB1PERIPH_BASE + 0x0400]
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set TIM4_BASE [expr $APB1PERIPH_BASE + 0x0800]
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set TIM5_BASE [expr $APB1PERIPH_BASE + 0x0C00]
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set TIM6_BASE [expr $APB1PERIPH_BASE + 0x1000]
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set TIM7_BASE [expr $APB1PERIPH_BASE + 0x1400]
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set RTC_BASE [expr $APB1PERIPH_BASE + 0x2800]
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set WWDG_BASE [expr $APB1PERIPH_BASE + 0x2C00]
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set IWDG_BASE [expr $APB1PERIPH_BASE + 0x3000]
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set SPI2_BASE [expr $APB1PERIPH_BASE + 0x3800]
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set SPI3_BASE [expr $APB1PERIPH_BASE + 0x3C00]
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set USART2_BASE [expr $APB1PERIPH_BASE + 0x4400]
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set USART3_BASE [expr $APB1PERIPH_BASE + 0x4800]
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set UART4_BASE [expr $APB1PERIPH_BASE + 0x4C00]
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set UART5_BASE [expr $APB1PERIPH_BASE + 0x5000]
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set I2C1_BASE [expr $APB1PERIPH_BASE + 0x5400]
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set I2C2_BASE [expr $APB1PERIPH_BASE + 0x5800]
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set CAN_BASE [expr $APB1PERIPH_BASE + 0x6400]
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set BKP_BASE [expr $APB1PERIPH_BASE + 0x6C00]
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set PWR_BASE [expr $APB1PERIPH_BASE + 0x7000]
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set DAC_BASE [expr $APB1PERIPH_BASE + 0x7400]
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set AFIO_BASE [expr $APB2PERIPH_BASE + 0x0000]
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set EXTI_BASE [expr $APB2PERIPH_BASE + 0x0400]
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set GPIOA_BASE [expr $APB2PERIPH_BASE + 0x0800]
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set GPIOB_BASE [expr $APB2PERIPH_BASE + 0x0C00]
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set GPIOC_BASE [expr $APB2PERIPH_BASE + 0x1000]
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set GPIOD_BASE [expr $APB2PERIPH_BASE + 0x1400]
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set GPIOE_BASE [expr $APB2PERIPH_BASE + 0x1800]
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set GPIOF_BASE [expr $APB2PERIPH_BASE + 0x1C00]
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set GPIOG_BASE [expr $APB2PERIPH_BASE + 0x2000]
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set ADC1_BASE [expr $APB2PERIPH_BASE + 0x2400]
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set ADC2_BASE [expr $APB2PERIPH_BASE + 0x2800]
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set TIM1_BASE [expr $APB2PERIPH_BASE + 0x2C00]
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set SPI1_BASE [expr $APB2PERIPH_BASE + 0x3000]
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set TIM8_BASE [expr $APB2PERIPH_BASE + 0x3400]
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set USART1_BASE [expr $APB2PERIPH_BASE + 0x3800]
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set ADC3_BASE [expr $APB2PERIPH_BASE + 0x3C00]
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set SDIO_BASE [expr $PERIPH_BASE + 0x18000]
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set DMA1_BASE [expr $AHBPERIPH_BASE + 0x0000]
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set DMA1_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0008]
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set DMA1_Channel2_BASE [expr $AHBPERIPH_BASE + 0x001C]
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set DMA1_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0030]
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set DMA1_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0044]
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set DMA1_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0058]
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set DMA1_Channel6_BASE [expr $AHBPERIPH_BASE + 0x006C]
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set DMA1_Channel7_BASE [expr $AHBPERIPH_BASE + 0x0080]
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set DMA2_BASE [expr $AHBPERIPH_BASE + 0x0400]
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set DMA2_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0408]
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set DMA2_Channel2_BASE [expr $AHBPERIPH_BASE + 0x041C]
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set DMA2_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0430]
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set DMA2_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0444]
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set DMA2_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0458]
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set RCC_BASE [expr $AHBPERIPH_BASE + 0x1000]
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set CRC_BASE [expr $AHBPERIPH_BASE + 0x3000]
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# /*Flash registers base address */
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set FLASH_R_BASE [expr $AHBPERIPH_BASE + 0x2000]
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# /*Flash Option Bytes base address */
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set OB_BASE 0x1FFFF800
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# /*FSMC Bankx registers base address */
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set FSMC_Bank1_R_BASE [expr $FSMC_R_BASE + 0x0000]
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set FSMC_Bank1E_R_BASE [expr $FSMC_R_BASE + 0x0104]
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set FSMC_Bank2_R_BASE [expr $FSMC_R_BASE + 0x0060]
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set FSMC_Bank3_R_BASE [expr $FSMC_R_BASE + 0x0080]
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set FSMC_Bank4_R_BASE [expr $FSMC_R_BASE + 0x00A0]
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# /*Debug MCU registers base address */
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set DBGMCU_BASE 0xE0042000
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# /*System Control Space memory map */
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set SCS_BASE 0xE000E000
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set SysTick_BASE [expr $SCS_BASE + 0x0010]
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set NVIC_BASE [expr $SCS_BASE + 0x0100]
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set SCB_BASE [expr $SCS_BASE + 0x0D00]
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