Darius Rad 00b591a09a Add 'riscv set_ir' command to set IR value for JTAG registers. ... This allows using different TAP addresses, for example, if using BSCANE2 primitives on a Xilinx FPGA.		2019-01-09 17:20:39 -05:00
..
manual	doc: fix several typos within manual documents	2018-05-09 11:43:23 +01:00
Makefile.am	Convert to non-recursive make	2016-12-08 16:23:10 +00:00
fdl.texi	- update openocd.texi to fdl 1.2	2008-02-29 18:10:46 +00:00
openocd.1	docs: update incorrect urls	2013-03-28 23:24:40 +00:00
openocd.texi	Add 'riscv set_ir' command to set IR value for JTAG registers.	2019-01-09 17:20:39 -05:00