133 lines
4.4 KiB
C
133 lines
4.4 KiB
C
/***************************************************************************
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* Copyright (C) 2005, 2006 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2007,2008 Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef EMBEDDED_ICE_H
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#define EMBEDDED_ICE_H
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#include "target.h"
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#include "register.h"
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#include "arm_jtag.h"
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#include "arm7_9_common.h"
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enum
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{
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EICE_DBG_CTRL = 0,
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EICE_DBG_STAT = 1,
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EICE_COMMS_CTRL = 2,
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EICE_COMMS_DATA = 3,
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EICE_W0_ADDR_VALUE = 4,
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EICE_W0_ADDR_MASK = 5,
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EICE_W0_DATA_VALUE = 6,
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EICE_W0_DATA_MASK = 7,
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EICE_W0_CONTROL_VALUE = 8,
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EICE_W0_CONTROL_MASK = 9,
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EICE_W1_ADDR_VALUE = 10,
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EICE_W1_ADDR_MASK = 11,
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EICE_W1_DATA_VALUE = 12,
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EICE_W1_DATA_MASK = 13,
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EICE_W1_CONTROL_VALUE = 14,
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EICE_W1_CONTROL_MASK = 15,
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EICE_VEC_CATCH = 16
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};
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enum
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{
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EICE_DBG_CONTROL_ICEDIS = 5,
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EICE_DBG_CONTROL_MONEN = 4,
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EICE_DBG_CONTROL_INTDIS = 2,
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EICE_DBG_CONTROL_DBGRQ = 1,
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EICE_DBG_CONTROL_DBGACK = 0,
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};
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enum
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{
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EICE_DBG_STATUS_IJBIT = 5,
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EICE_DBG_STATUS_ITBIT = 4,
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EICE_DBG_STATUS_SYSCOMP = 3,
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EICE_DBG_STATUS_IFEN = 2,
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EICE_DBG_STATUS_DBGRQ = 1,
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EICE_DBG_STATUS_DBGACK = 0
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};
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enum
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{
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EICE_W_CTRL_ENABLE = 0x100,
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EICE_W_CTRL_RANGE = 0x80,
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EICE_W_CTRL_CHAIN = 0x40,
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EICE_W_CTRL_EXTERN = 0x20,
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EICE_W_CTRL_nTRANS = 0x10,
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EICE_W_CTRL_nOPC = 0x8,
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EICE_W_CTRL_MAS = 0x6,
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EICE_W_CTRL_ITBIT = 0x2,
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EICE_W_CTRL_nRW = 0x1
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};
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enum
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{
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EICE_COMM_CTRL_WBIT = 1,
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EICE_COMM_CTRL_RBIT = 0
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};
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typedef struct embeddedice_reg_s
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{
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int addr;
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arm_jtag_t *jtag_info;
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} embeddedice_reg_t;
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extern reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9);
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extern int embeddedice_setup(target_t *target);
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extern int embeddedice_read_reg(reg_t *reg);
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extern void embeddedice_write_reg(reg_t *reg, u32 value);
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extern int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);
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extern void embeddedice_store_reg(reg_t *reg);
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extern void embeddedice_set_reg(reg_t *reg, u32 value);
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extern int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
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extern int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size);
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extern int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size);
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extern int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout);
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/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of
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* embeddedice_write_reg
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*/
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static const int embeddedice_num_bits[]={32,5,1};
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static __inline__ void embeddedice_write_reg_inner( jtag_tap_t *tap, int reg_addr, u32 value)
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{
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u32 values[3];
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values[0]=value;
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values[1]=reg_addr;
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values[2]=1;
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jtag_add_dr_out( tap,
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3,
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embeddedice_num_bits,
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values,
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-1);
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}
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void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count);
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#endif /* EMBEDDED_ICE_H */
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