132 lines
3.4 KiB
INI
132 lines
3.4 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# script for stm32l5x family
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#
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# stm32l5 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32l5x
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 64kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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# See STM Document RM0438
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# RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
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# Corresponds to Cortex®-M33 JTAG debug port ID code
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set _CPUTAPID 0x0ba04477
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} {
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# SWD IDCODE (single drop, arm)
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set _CPUTAPID 0x0be12477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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# use non-secure RAM by default
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# declare non-secure flash
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flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
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# Common knowledges tells JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
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# the safe side.
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#
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# Note that there is a pretty wide band where things are
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# more or less stable, see http://openocd.zylin.com/#/c/3366/
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adapter speed 500
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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proc clock_config_110_mhz {} {
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# MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
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# RCC_APB1ENR1 = PWREN
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mww 0x40021058 0x10000000
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# delay for register clock enable (read back reg)
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mrw 0x40021058
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# PWR_CR1 : VOS Range 0
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mww 0x40007000 0
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# while (PWR_SR2 & VOSF)
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while {([mrw 0x40007014] & 0x0400)} {}
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# FLASH_ACR : 5 WS for 110 MHz HCLK
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mww 0x40022000 0x00000005
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# RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz
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# fVCO = 4 x 55 /1 = 220
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# SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz
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mww 0x4002100C 0x01003711
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# RCC_CR |= PLLON
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mmw 0x40021000 0x01000000 0
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# while !(RCC_CR & PLLRDY)
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while {!([mrw 0x40021000] & 0x02000000)} {}
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# RCC_CFGR |= SW_PLL
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mmw 0x40021008 0x00000003 0
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# while ((RCC_CFGR & SWS) != PLL)
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while {([mrw 0x40021008] & 0x0C) != 0x0C} {}
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}
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$_TARGETNAME configure -event reset-init {
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clock_config_110_mhz
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# Boost JTAG frequency
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adapter speed 4000
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}
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$_TARGETNAME configure -event reset-start {
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# Reset clock is MSI (4 MHz)
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adapter speed 480
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}
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$_TARGETNAME configure -event examine-end {
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
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mmw 0xE0044004 0x00000006 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE0044008 0x00001800 0
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}
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$_TARGETNAME configure -event trace-config {
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# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
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# change this value accordingly to configure trace pins
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# assignment
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mmw 0xE0044004 0x00000020 0
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}
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