171 lines
6.0 KiB
INI
171 lines
6.0 KiB
INI
#
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# Glyn Tonga2 SO-DIMM CPU module (Toshiba TMPA900CMXBG, ARM9)
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#
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# http://toshiba-mikrocontroller.de/sites/TMPA900CPUBOARDStarter.htm
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#
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# Hardware on the S0-DIMM module:
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# - Toshiba TMPA900CMXBG (ARM9, ARM926EJ-S, max. 200MHz)
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# - DDR SDRAM: Hynix H5MS5162DFR-J3M (64Mbyte, x16, 1.8V, 166/83MHz at CL3/2)
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# - NAND flash: Samsung K9F2G08U0B-PIB0 (256M x 8 Bit, 3.3V)
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# - Ethernet: SMSC LAN9221I-ABZJ (10/100Mbit, Non-PCI, 16 bit interface)
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#
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source [find target/tmpa900.cfg]
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########################
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# Target configuration #
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########################
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$_TARGETNAME configure -event reset-init { tonga2_init }
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proc tonga2_init { } {
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######################
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# PLL initialization #
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######################
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# Clock overview (see datasheet chapter 3.5.2, page 57):
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# - fs: Low-frequency oscillator
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# - fOSCH: High-frequency oscillator (24MHz on this board)
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# - fPLL = fOSCH * multiplier (where multiplier can be 6 or 8)
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# - fFCLK = fPLL / gear (where gear can be 1/2/4/8)
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# - fHCLK is always fFCLK/2. fPCLK is also fFCLK/2.
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#
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# We select multiplier = 8 and gear = 1, so
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# fFCLK = fOSCH * 8 / 1 = 192MHz.
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# SYSCR3 (System Control Register 3): Disable and configure PLL.
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# - PLL operation control: off
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# - PLL constant value setting 1: always 0, as per datasheet
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# - PLL constant value setting 2: x8 (multiplier = 8)
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mww 0xf005000c 0x00000007
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# SYSCR4 (System Control Register 4): Configure PLL.
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# - PLL constant value setting 3: 140MHz or more
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# - PLL constant value setting 4: always 1, as per datasheet
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# - PLL constant value setting 5: 140MHz or more
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mww 0xf0050010 0x00000065
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# SYSCR3 (System Control Register 3): Enable PLL.
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# - PLL operation control: on
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# - All other bits remain set as above.
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mww 0xf005000c 0x00000087
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# Wait for PLL to stabilize.
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sleep 10
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# SYSCR2 (System Control Register 2): Switch from fOSCH to fPLL.
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# - Selection of the PLL output clock: fPLL
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mww 0xf0050008 0x00000002
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# SYSCR1 (System Control Register 1):
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# - Clock gear programming: fc/1 (i.e., gear = 1, don't divide).
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mww 0xf0050004 0x00000000
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# CLKCR5 (Clock Control Register 5): Set bits 3 and 6. The datasheet
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# says the bits are reserved, but also recommends "Write as one".
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mww 0xf0050054 0x00000048
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##############################################################
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# Dynamic Memory Controller (DMC) / DDR SDRAM initialization #
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##############################################################
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# PMC (Power Management Controller):
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# PMCDRV (External Port "Driverbility" control register):
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# Bits DRV_MEM0/DRV_MEM1 (memory relation port drive power):
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mww 0xf0020260 0x00000003 ;# Select 1.8V +/- 0.1V
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# Setup DDR SDRAM timing parameters for our specific chip.
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mww 0xf4310014 0x00000004 ;# cas_latency = 2
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mww 0xf4310018 0x00000001 ;# t_dqss = 1
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mww 0xf431001c 0x00000002 ;# t_mrd = 2
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mww 0xf4310020 0x0000000a ;# t_ras = 10
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mww 0xf4310024 0x0000000a ;# t_rc = 10
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mww 0xf4310028 0x00000013 ;# t_rcd = 3, schedule_rcd = 2
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mww 0xf431002c 0x0000010a ;# t_rfc = 10, schedule_rfc = 8
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mww 0xf4310030 0x00000013 ;# t_rp = 3, schedule_rp = 2
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mww 0xf4310034 0x00000002 ;# t_rrd = 2
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mww 0xf4310038 0x00000002 ;# t_wr = 2
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mww 0xf431003c 0x00000001 ;# t_wtr = 1
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mww 0xf4310040 0x0000000a ;# t_xp = 10
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mww 0xf4310044 0x0000000c ;# t_xsr = 12
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mww 0xf4310048 0x00000014 ;# t_esr = 20
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# dmc_memory_cfg_5 (DMC Memory Configuration register):
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# Set memory configuration:
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# column_bits = 10, row_bits = 13, ap-bit = 10, power_down_prd = 0,
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# auto_power_down = disable, stop_mem_clock = disable, memory_burst = 4
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mww 0xf431000c 0x00010012
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# dmc_user_config_5 (DMC user_config register):
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# Data bus width of DDR SDRAM: 16 bit
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mww 0xf4310304 0x00000058
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# dmc_refresh_prd_5 (DMC Refresh Period register):
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# Auto refresh: every 2656 (0xa60) DMCSCLK periods.
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mww 0xf4310010 0x00000a60
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# dmc_chip_0_cfg_5 (DMC chip_0_cfg registers):
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# - SDRAM address structure: bank, row, column
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# - address_match = 01000000 (start address [31:24])
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# - address_mask = 11111100 (start address [31:24] mask value)
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mww 0xf4310200 0x000140fc
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# Initialize the DDR SDRAM chip.
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# dmc_direct_cmd_5 (DMC Direct Command register).
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# See datasheet chapter 3.10.5.1, page 268.
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mww 0xf4310008 0x000c0000 ;# RAM init: NOP
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mww 0xf4310008 0x00000000 ;# RAM init: Precharge all
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mww 0xf4310008 0x00040000 ;# RAM init: Autorefresh
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mww 0xf4310008 0x00040000 ;# RAM init: Autorefresh
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mww 0xf4310008 0x00080032 ;# RAM init: addr_13_to_0 = 0x32
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mww 0xf4310008 0x000c0000 ;# RAM init: NOP
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mww 0xf4310008 0x000a0000 ;# RAM init: bank_addr = bank 2
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# dmc_id_<0-5>_cfg_5 (DMC id_<0-5>_cfg registers):
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# Set min./max. QoS values.
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# - 0x5: Enable QoS, max. QoS = 1
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# - 0xb: Enable QoS, min. QoS = 2
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mww 0xf4310100 0x00000005 ;# AHB0: CPU Data
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mww 0xf4310104 0x00000005 ;# AHB1: CPU Inst
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mww 0xf4310108 0x0000000b ;# AHB2: LCDC
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mww 0xf431010c 0x00000005 ;# AHB3: LCDDA, USB
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mww 0xf4310110 0x00000005 ;# AHB4: DMA1
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mww 0xf4310114 0x00000005 ;# AHB5: DMA2
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# dmc_memc_cmd_5 (DMC Memory Controller Command register):
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# Change DMC state to ready.
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mww 0xf4310004 0x00000000 ;# memc_cmd = "Go"
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# EBI: SMC Timeout register
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mww 0xf00a0050 0x00000001 ;# smc_timeout = 1
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########################################################
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# Static Memory Controller (SMC) / SRAM initialization #
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########################################################
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# smc_set_cycles_5 (SMC Set Cycles register):
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# tRC = 10, tWC = 10, tCEOE = 7, tWP = 5, tPC=2, tTR=2
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mww 0xf4311014 0x0004afaa
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# smc_set_opmode_5 (SMC Set Opmode register):
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# Memory data bus width = 16 bits, async read mode, read burst
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# length = 1 beat, async write mode, write burst length = 1 beat,
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# byte enable (SMCBE0-1) timing = SMCCSn timing, memory burst boundary
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# split setting = burst can cross any address boundary
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mww 0xf4311018 0x00000001
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# smc_direct_cmd_5 (SMC Direct Command register):
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# cmd_type = UpdateRegs, chip_select = CS1
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mww 0xf4311010 0x00c00000
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}
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#######################
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# Flash configuration #
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#######################
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# TODO: Implement NAND support.
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