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riscv-openocd/testing/results/v0.4.0-rc1/LPC2148.html

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<html>
<head>
<title>Test results for revision 1.62</title>
</head>
<body>
<H1>LPC2148</H1>
<H2>Connectivity</H2>
<table border=1>
<tr>
<td>ID</td>
<td>Target</td>
<td>Interface</td>
<td>Description</td>
<td>Initial state</td>
<td>Input</td>
<td>Expected output</td>
<td>Actual output</td>
<td>Pass/Fail</td>
</tr>
<tr>
<td><a name="CON001"/>CON001</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Telnet connection</td>
<td>Power on, jtag target attached</td>
<td>On console, type<br><code>telnet ip port</code></td>
<td><code>Open On-Chip Debugger<br>></code></td>
<td><code>Open On-Chip Debugger<br>></code></td>
<td>PASS</td>
</tr>
<tr>
<td><a name="CON002"/>CON002</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>GDB server connection</td>
<td>Power on, jtag target attached</td>
<td>On GDB console, type<br><code>target remote ip:port</code></td>
<td><code>Remote debugging using 10.0.0.73:3333</code></td>
<td><code>
(gdb) tar remo 10.0.0.73:3333<br>
Remote debugging using 10.0.0.73:3333<br>
0x00000000 in ?? ()<br>
</code></td>
<td>PASS</td>
</tr>
</table>
<H2>Reset</H2>
<table border=1>
<tr>
<td>ID</td>
<td>Target</td>
<td>Interface</td>
<td>Description</td>
<td>Initial state</td>
<td>Input</td>
<td>Expected output</td>
<td>Actual output</td>
<td>Pass/Fail</td>
</tr>
<tr>
<td><a name="RES001"/>RES001</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Reset halt on a blank target</td>
<td>Erase all the content of the flash</td>
<td>Connect via the telnet interface and type <br><code>reset halt</code></td>
<td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
<td>
<code>
> mdw 0 32<br>
0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
> reset halt<br>
JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
target state: halted<br>
target halted in Thumb state due to debug-request, current mode: Supervisor<br>
cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
>
</code>
</td>
<td>PASS</td>
</tr>
<tr>
<td><a name="RES002"/>RES002</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Reset init on a blank target</td>
<td>Erase all the content of the flash</td>
<td>Connect via the telnet interface and type <br><code>reset init</code></td>
<td>Reset should return without error and the output should contain <br><code>executing reset script 'name_of_the_script'</code></td>
<td>
<code>
> reset init<br>
JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
target state: halted<br>
target halted in Thumb state due to debug-request, current mode: Supervisor<br>
cpsr: 0xa00000f3 pc: 0x7fffd2da<br>
core state: ARM<br>
>
</code>
</td>
<td>PASS<br>
NOTE! Even if there is no message, the reset script is being executed (proved by side effects)</td>
</tr>
<tr>
<td><a name="RES003"/>RES003</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Reset after a power cycle of the target</td>
<td>Reset the target then power cycle the target</td>
<td>Connect via the telnet interface and type <br><code>reset halt</code> after the power was detected</td>
<td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
<td>
<code>
nsed nSRST asserted.<br>
nsed power dropout.<br>
nsed power restore.<br>
SRST took 186ms to deassert<br>
JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
target state: halted<br>
target halted in Thumb state due to debug-request, current mode: Supervisor<br>
cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
core state: ARM<br>
> reset halt<br>
JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
target state: halted<br>
target halted in Thumb state due to debug-request, current mode: Supervisor<br>
cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
>
</code>
</td>
<td>PASS</td>
</tr>
<tr>
<td><a name="RES004"/>RES004</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Reset halt on a blank target where reset halt is supported</td>
<td>Erase all the content of the flash</td>
<td>Connect via the telnet interface and type <br><code>reset halt</code></td>
<td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>
<td>
<code>
> reset halt<br>
JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
target state: halted<br>
target halted in Thumb state due to debug-request, current mode: Supervisor<br>
cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
>
</code>
</td>
<td>PASS</td>
</tr>
<tr>
<td><a name="RES005"/>RES005</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Reset halt on a blank target using return clock</td>
<td>Erase all the content of the flash, set the configuration script to use RCLK</td>
<td>Connect via the telnet interface and type <br><code>reset halt</code></td>
<td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
<td>
<code>
> jtag_khz 0<br>
RCLK - adaptive<br>
> reset init<br>
JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
target state: halted<br>
target halted in Thumb state due to debug-request, current mode: Supervisor<br>
cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
core state: ARM<br>
>
</code>
</td>
<td>PASS</td>
</tr>
</table>
<H2>JTAG Speed</H2>
<table border=1>
<tr>
<td>ID</td>
<td>Target</td>
<td>ZY1000</td>
<td>Description</td>
<td>Initial state</td>
<td>Input</td>
<td>Expected output</td>
<td>Actual output</td>
<td>Pass/Fail</td>
</tr>
<tr>
<td><a name="SPD001"/>SPD001</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>16MHz on normal operation</td>
<td>Reset init the target according to RES002 </td>
<td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
<td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
<td>
<code>
> jtag_khz 16000<br>
jtag_speed 4 => JTAG clk=16.000000<br>
16000 kHz<br>
> reset halt<br>
JTAG scan chain interrogation failed: all zeroes<br>
Check JTAG interface, timings, target power, etc.<br>
error: -100<br>
Command handler execution failed<br>
in procedure 'reset' called at file "command.c", line 638<br>
called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352<br>
invalid mode value encountered 0<br>
cpsr contains invalid mode value - communication failure<br>
ThumbEE -- incomplete support<br>
target state: halted<br>
target halted in ThumbEE state due to debug-request, current mode: System<br>
cpsr: 0x1fffffff pc: 0xfffffffa<br>
invalid mode value encountered 0<br>
cpsr contains invalid mode value - communication failure<br>
target state: halted<br>
target halted in Thumb state due to debug-request, current mode: System<br>
cpsr: 0xc00003ff pc: 0xfffffff0<br>
invalid mode value encountered 0<br>
cpsr contains invalid mode value - communication failure<br>
invalid mode value encountered 0<br>
cpsr contains invalid mode value - communication failure<br>
invalid mode value encountered 0<br>
cpsr contains invalid mode value - communication failure<br>
invalid mode value encountered 0<br>
cpsr contains invalid mode value - communication failure<br>
ThumbEE -- incomplete support<br>
target state: halted<br>
target halted in ThumbEE state due to debug-request, current mode: System<br>
cpsr: 0xffffffff pc: 0xfffffffa<br>
>
</code>
</td>
<td><font color=red><b>FAIL</b></font></td>
</tr>
<tr>
<td><a name="SPD002"/>SPD002</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>8MHz on normal operation</td>
<td>Reset init the target according to RES002 </td>
<td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
<td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
<td>
<code>
> jtag_khz 8000<br>
jtag_speed 8 => JTAG clk=8.000000<br>
8000 kHz<br>
> reset halt<br>
JTAG scan chain interrogation failed: all zeroes<br>
Check JTAG interface, timings, target power, etc.<br>
error: -100<br>
Command handler execution failed<br>
in procedure 'reset' called at file "command.c", line 638<br>
called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352<br>
invalid mode value encountered 0<br>
cpsr contains invalid mode value - communication failure<br>
invalid mode value encountered 0<br>
cpsr contains invalid mode value - communication failure<br>
>
</code>
</td>
<td><font color=red><b>FAIL</b></font></td>
</tr>
<tr>
<td><a name="SPD003"/>SPD003</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>4MHz on normal operation</td>
<td>Reset init the target according to RES002 </td>
<td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
<td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
<td>
<code>
> jtag_khz 4000<br>
jtag_speed 16 => JTAG clk=4.000000<br>
4000 kHz<br>
> reset halt<br>
JTAG tap: lpc2148.cpu tap/device found: 0xc79f0f87 (mfg: 0x7c3, part: 0x79f0, ver: 0xc)<br>
JTAG tap: lpc2148.cpu UNEXPECTED: 0xc79f0f87 (mfg: 0x7c3, part: 0x79f0, ver: 0xc)<br>
JTAG tap: lpc2148.cpu expected 1 of 1: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
Unexpected idcode after end of chain: 64 0x0000007f<br>
Unexpected idcode after end of chain: 160 0x0000007f<br>
Unexpected idcode after end of chain: 192 0x0000007f<br>
Unexpected idcode after end of chain: 320 0x0000007f<br>
Unexpected idcode after end of chain: 352 0x0000007f<br>
Unexpected idcode after end of chain: 384 0x0000007f<br>
Unexpected idcode after end of chain: 480 0x0000007f<br>
Unexpected idcode after end of chain: 512 0x0000007f<br>
Unexpected idcode after end of chain: 544 0x0000007f<br>
double-check your JTAG setup (interface, speed, missing TAPs, ...)<br>
error: -100<br>
Command handler execution failed<br>
in procedure 'reset' called at file "command.c", line 638<br>
called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352<br>
>
</code>
</td>
<td><font color=red><b>FAIL</b></font></td>
</tr>
<tr>
<td><a name="SPD004"/>SPD004</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>2MHz on normal operation</td>
<td>Reset init the target according to RES002 </td>
<td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
<td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
<td>
<code>
> jtag_khz 2000<br>
jtag_speed 32 => JTAG clk=2.000000<br>
2000 kHz<br>
> reset halt<br>
JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
target state: halted<br>
target halted in Thumb state due to debug-request, current mode: Supervisor<br>
cpsr: 0xa00000f3 pc: 0x7fffd2da<br>
> mdw 0 32<br>
0x00000000: e59f4034 e3a05002 e5845000 e3a05003 e5845004 e59f201c e3a03000 e1020093<br>
0x00000020: e2822028 e1021093 e3c03007 e5023028 e51ff004 7fffd1c4 e002c014 e01fc000<br>
0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
>
</code>
</td>
<td>PASS</td>
</tr>
<tr>
<td><a name="SPD005"/>SPD005</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>RCLK on normal operation</td>
<td>Reset init the target according to RES002 </td>
<td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
<td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
<td>
<code>
> jtag_khz 0<br>
RCLK - adaptive<br>
> mdw 0 32<br>
0x00000000: e59f4034 e3a05002 e5845000 e3a05003 e5845004 e59f201c e3a03000 e1020093<br>
0x00000020: e2822028 e1021093 e3c03007 e5023028 e51ff004 7fffd1c4 e002c014 e01fc000<br>
0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
>
</code>
</td>
<td>PASS</td>
</tr>
</table>
<H2>Debugging</H2>
<table border=1>
<tr>
<td>ID</td>
<td>Target</td>
<td>Interface</td>
<td>Description</td>
<td>Initial state</td>
<td>Input</td>
<td>Expected output</td>
<td>Actual output</td>
<td>Pass/Fail</td>
</tr>
<tr>
<td><a name="DBG001"/>DBG001</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Load is working</td>
<td>Reset init is working, RAM is accesible, GDB server is started</td>
<td>On the console of the OS: <br>
<code>arm-elf-gdb test_ram.elf</code><br>
<code>(gdb) target remote ip:port</code><br>
<code>(gdb) load</load>
</td>
<td>Load should return without error, typical output looks like:<br>
<code>
Loading section .text, size 0x14c lma 0x0<br>
Start address 0x40, load size 332<br>
Transfer rate: 180 bytes/sec, 332 bytes/write.<br>
</code>
</td>
<td><code>
(gdb) load<br>
Loading section .text, size 0x16c lma 0x40000000<br>
Start address 0x40000040, load size 364<br>
Transfer rate: 32 KB/sec, 364 bytes/write.<br>
(gdb)
</code></td>
<td>PASS</td>
</tr>
<tr>
<td><a name="DBG002"/>DBG002</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Software breakpoint</td>
<td>Load the test_ram.elf application, use instructions from GDB001</td>
<td>In the GDB console:<br>
<code>
(gdb) monitor gdb_breakpoint_override soft<br>
software breakpoints enabled<br>
(gdb) break main<br>
Breakpoint 1 at 0xec: file src/main.c, line 71.<br>
(gdb) continue<br>
Continuing.
</code>
</td>
<td>The software breakpoint should be reached, a typical output looks like:<br>
<code>
target state: halted<br>
target halted in ARM state due to breakpoint, current mode: Supervisor<br>
cpsr: 0x000000d3 pc: 0x000000ec<br>
<br>
Breakpoint 1, main () at src/main.c:71<br>
71 DWORD a = 1;
</code>
</td>
<td>
<code>
(gdb) monitor gdb_breakpoint_override soft<br>
force soft breakpoints<br>
Current language: auto<br>
The current source language is "auto; currently asm".<br>
(gdb) break main<br>
Breakpoint 1 at 0x4000010c: file src/main.c, line 71.<br>
(gdb) c<br>
Continuing.<br>
<br>
Breakpoint 1, main () at src/main.c:71<br>
71 DWORD a = 1;<br>
Current language: auto<br>
The current source language is "auto; currently c".<br>
(gdb)
</code>
</td>
<td>PASS</td>
</tr>
<tr>
<td><a name="DBG003"/>DBG003</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Single step in a RAM application</td>
<td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
<td>In GDB, type <br><code>(gdb) step</code></td>
<td>The next instruction should be reached, typical output:<br>
<code>
(gdb) step<br>
target state: halted<br>
target halted in ARM state due to single step, current mode: Abort<br>
cpsr: 0x20000097 pc: 0x000000f0<br>
target state: halted<br>
target halted in ARM state due to single step, current mode: Abort<br>
cpsr: 0x20000097 pc: 0x000000f4<br>
72 DWORD b = 2;
</code>
</td>
<td>
<code>
(gdb) step<br>
72 DWORD b = 2;<br>
(gdb)
</code>
</td>
<td>PASS</td>
</tr>
<tr>
<td><a name="DBG004"/>DBG004</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Software break points are working after a reset</td>
<td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
<td>In GDB, type <br><code>
(gdb) monitor reset init<br>
(gdb) load<br>
(gdb) continue<br>
</code></td>
<td>The breakpoint should be reached, typical output:<br>
<code>
target state: halted<br>
target halted in ARM state due to breakpoint, current mode: Supervisor<br>
cpsr: 0x000000d3 pc: 0x000000ec<br>
<br>
Breakpoint 1, main () at src/main.c:71<br>
71 DWORD a = 1;
</code>
</td>
<td><code>
(gdb) moni reset init<br>
JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
target state: halted<br>
target halted in Thumb state due to debug-request, current mode: Supervisor<br>
cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
core state: ARM<br>
(gdb) load<br>
Loading section .text, size 0x16c lma 0x40000000<br>
Start address 0x40000040, load size 364<br>
Transfer rate: 27 KB/sec, 364 bytes/write.<br>
(gdb) c<br>
Continuing.<br>
<br>
Breakpoint 1, main () at src/main.c:71<br>
71 DWORD a = 1;<br>
(gdb)
</code></td>
<td>PASS</td>
</tr>
<tr>
<td><a name="DBG005"/>DBG005</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Hardware breakpoint</td>
<td>Flash the test_rom.elf application. Make this test after FLA004 has passed</td>
<td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
<code>
(gdb) monitor reset init<br>
(gdb) load<br>
Loading section .text, size 0x194 lma 0x100000<br>
Start address 0x100040, load size 404<br>
Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
(gdb) monitor gdb_breakpoint_override hard<br>
force hard breakpoints<br>
(gdb) break main<br>
Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
(gdb) continue<br>
</code>
</td>
<td>The breakpoint should be reached, typical output:<br>
<code>
Continuing.<br>
<br>
Breakpoint 1, main () at src/main.c:69<br>
69 DWORD a = 1;<br>
</code>
</td>
<td>
<code>
(gdb) monitor gdb_breakpoint_override hard<br>
force hard breakpoints<br>
(gdb) break main<br>
Breakpoint 1 at 0x10c: file src/main.c, line 71.<br>
(gdb) continue<br>
Continuing.<br>
Note: automatically using hardware breakpoints for read-only addresses.<br>
<br>
Breakpoint 1, main () at src/main.c:71<br>
71 DWORD a = 1;<br>
Current language: auto<br>
The current source language is "auto; currently c".<br>
(gdb)
</code>
</td>
<td>PASS <font color=red>NOTE: This test is failing from time to time, not able to describe a cause</font></td>
</tr>
<tr>
<td><a name="DBG006"/>DBG006</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Hardware breakpoint is set after a reset</td>
<td>Follow the instructions to flash and insert a hardware breakpoint from DBG005</td>
<td>In GDB, type <br>
<code>
(gdb) monitor reset<br>
(gdb) monitor reg pc 0x100000<br>
pc (/32): 0x00100000<br>
(gdb) continue
</code><br>
where the value inserted in PC is the start address of the application
</td>
<td>The breakpoint should be reached, typical output:<br>
<code>
Continuing.<br>
<br>
Breakpoint 1, main () at src/main.c:69<br>
69 DWORD a = 1;<br>
</code>
</td>
<td>
<code>
(gdb) monitor reset init<br>
JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
target state: halted<br>
target halted in ARM state due to debug-request, current mode: Supervisor<br>
cpsr: 0x60000013 pc: 0x00000160<br>
core state: ARM<br>
(gdb) monitor reg pc 0x40<br>
pc (/32): 0x00000040<br>
(gdb) continue<br>
Continuing.<br>
<br>
Breakpoint 1, main () at src/main.c:71<br>
71 DWORD a = 1;<br>
(gdb)
</code>
</td>
<td>PASS</td>
</tr>
<tr>
<td><a name="DBG007"/>DBG007</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Single step in ROM</td>
<td>Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed</td>
<td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
<code>
(gdb) monitor reset<br>
(gdb) load<br>
Loading section .text, size 0x194 lma 0x100000<br>
Start address 0x100040, load size 404<br>
Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
(gdb) monitor gdb_breakpoint_override hard<br>
force hard breakpoints<br>
(gdb) break main<br>
Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
(gdb) continue<br>
Continuing.<br>
<br>
Breakpoint 1, main () at src/main.c:69<br>
69 DWORD a = 1;<br>
(gdb) step
</code>
</td>
<td>The breakpoint should be reached, typical output:<br>
<code>
target state: halted<br>
target halted in ARM state due to single step, current mode: Supervisor<br>
cpsr: 0x60000013 pc: 0x0010013c<br>
70 DWORD b = 2;<br>
</code>
</td>
<td><code>
(gdb) load<br>
Loading section .text, size 0x16c lma 0x0<br>
Start address 0x40, load size 364<br>
Transfer rate: 637 bytes/sec, 364 bytes/write.<br>
(gdb) monitor gdb_breakpoint_override hard<br>
force hard breakpoints<br>
Current language: auto<br>
The current source language is "auto; currently asm".<br>
(gdb) break main<br>
Breakpoint 1 at 0x10c: file src/main.c, line 71.<br>
(gdb) continue<br>
Continuing.<br>
Note: automatically using hardware breakpoints for read-only addresses.<br>
<br>
Breakpoint 1, main () at src/main.c:71<br>
71 DWORD a = 1;<br>
Current language: auto<br>
The current source language is "auto; currently c".<br>
(gdb) step<br>
72 DWORD b = 2;<br>
(gdb)
</code></td>
<td>PASS</td>
</tr>
</table>
<H2>RAM access</H2>
Note: these tests are not designed to test/debug the target, but to test functionalities!
<table border=1>
<tr>
<td>ID</td>
<td>Target</td>
<td>Interface</td>
<td>Description</td>
<td>Initial state</td>
<td>Input</td>
<td>Expected output</td>
<td>Actual output</td>
<td>Pass/Fail</td>
</tr>
<tr>
<td><a name="RAM001"/>RAM001</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>32 bit Write/read RAM</td>
<td>Reset init is working</td>
<td>On the telnet interface<br>
<code> > mww ram_address 0xdeadbeef 16<br>
> mdw ram_address 32
</code>
</td>
<td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.<br>
<code>
> mww 0x0 0xdeadbeef 16<br>
> mdw 0x0 32<br>
0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388<br>
0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388<br>
</code>
</td>
<td><code>
> mww 0x40000000 0xdeadbeef 16<br>
> mdw 0x40000000 32<br>
0x40000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
0x40000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
0x40000040: e1a00000 e1a00000 e1a00000 e1a00000 e1a00000 e1a00000 e1a00000 e1a00000<br>
0x40000060: e321f0db e59fd07c e321f0d7 e59fd078 e321f0d1 e59fd074 e321f0d2 e59fd070<br>
>
</code></td>
<td>PASS</td>
</tr>
<tr>
<td><a name="RAM002"/>RAM002</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>16 bit Write/read RAM</td>
<td>Reset init is working</td>
<td>On the telnet interface<br>
<code> > mwh ram_address 0xbeef 16<br>
> mdh ram_address 32
</code>
</td>
<td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.<br>
<code>
> mwh 0x0 0xbeef 16<br>
> mdh 0x0 32<br>
0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000<br>
>
</code>
</td>
<td><code>
> mwh 0x40000000 0xbeef 16<br>
> mdh 0x40000000 32<br>
0x40000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
0x40000020: beef dead beef dead beef dead beef dead beef dead beef dead beef dead beef dead<br>
>
</code></td>
<td>PASS</td>
</tr>
<tr>
<td><a name="RAM003"/>RAM003</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>8 bit Write/read RAM</td>
<td>Reset init is working</td>
<td>On the telnet interface<br>
<code> > mwb ram_address 0xab 16<br>
> mdb ram_address 32
</code>
</td>
<td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.<br>
<code>
> mwb ram_address 0xab 16<br>
> mdb ram_address 32<br>
0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
>
</code>
</td>
<td><code>
> mwb 0x40000000 0xab 16
> mdb 0x40000000 32
0x40000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ef be ef be ef be ef be ef be ef be ef be ef be
>
</code></td>
<td>PASS</td>
</tr>
</table>
<H2>Flash access</H2>
<table border=1>
<tr>
<td>ID</td>
<td>Target</td>
<td>Interface</td>
<td>Description</td>
<td>Initial state</td>
<td>Input</td>
<td>Expected output</td>
<td>Actual output</td>
<td>Pass/Fail</td>
</tr>
<tr>
<td><a name="FLA001"/>FLA001</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Flash probe</td>
<td>Reset init is working</td>
<td>On the telnet interface:<br>
<code> > flash probe 0</code>
</td>
<td>The command should execute without error. The output should state the name of the flash and the starting address. An example of output:<br>
<code>flash 'ecosflash' found at 0x01000000</code>
</td>
<td>
<code>
> flash probe 0<br>
flash 'lpc2000' found at 0x00000000
</code>
</td>
<td>PASS</td>
</tr>
<tr>
<td><a name="FLA002"/>FLA002</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>flash fillw</td>
<td>Reset init is working, flash is probed</td>
<td>On the telnet interface<br>
<code> > flash fillw 0x1000000 0xdeadbeef 16
</code>
</td>
<td>The commands should execute without error. The output looks like:<br>
<code>
wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s)
</code><br>
To verify the contents of the flash:<br>
<code>
> mdw 0x1000000 32<br>
0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
</code>
</td>
<td><code>
> flash fillw 0x0 0xdeadbeef 16<br>
Verification will fail since checksum in image (0xdeadbeef) to be written to flash is different from calculated vector checksum (0xe93fc777).<br>
To remove this warning modify build tools on developer PC to inject correct LPC vector checksum.<br>
wrote 64 bytes to 0x00000000 in 0.040000s (1.563 kb/s)<br>
> mdw 0 32<br>
0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef e93fc777 deadbeef deadbeef<br>
0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
>
</code></td>
<td><font color=red>FAIL</font></td>
</tr>
<tr>
<td><a name="FLA003"/>FLA003</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Flash erase</td>
<td>Reset init is working, flash is probed</td>
<td>On the telnet interface<br>
<code> > flash erase_address 0x1000000 0x2000
</code>
</td>
<td>The commands should execute without error.<br>
<code>
erased address 0x01000000 length 8192 in 4.970000s
</code>
To check that the flash has been erased, read at different addresses. The result should always be 0xff.
<code>
> mdw 0x1000000 32<br>
0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
</code>
</td>
<td><code>
> flash erase_address 0 0x2000<br>
erased address 0x00000000 (length 8192) in 0.510000s (15.686 kb/s)<br>
> mdw 0 32<br>
0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
>
</code></td>
<td>PASS</td>
</tr>
<tr>
<td><a name="FLA004"/>FLA004</td>
<td>LPC2148</td>
<td>ZY1000</td>
<td>Loading to flash from GDB</td>
<td>Reset init is working, flash is probed, connectivity to GDB server is working</td>
<td>Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf. <br>
<code>
(gdb) target remote ip:port<br>
(gdb) monitor reset<br>
(gdb) load<br>
Loading section .text, size 0x194 lma 0x100000<br>
Start address 0x100040, load size 404<br>
Transfer rate: 179 bytes/sec, 404 bytes/write.
(gdb) monitor verify_image path_to_elf_file
</code>
</td>
<td>The output should look like:<br>
<code>
verified 404 bytes in 5.060000s
</code><br>
The failure message is something like:<br>
<code>Verify operation failed address 0x00200000. Was 0x00 instead of 0x18</code>
</td>
<td>
<code>
(gdb) moni verify_image /tftp/10.0.0.194/test_rom.elf<br>
checksum mismatch - attempting binary compare<br>
Verify operation failed address 0x00000014. Was 0x58 instead of 0x60<br>
<br>
Command handler execution failed<br>
in procedure 'verify_image' called at file "command.c", line 647<br>
called at file "command.c", line 361<br>
(gdb)
</code>
</td>
<td><font color=red>FAIL</font></td>
</tr>
</table>
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