49 lines
1.5 KiB
INI
49 lines
1.5 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# script for stm32l5x family
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# stm32l5x devices support both JTAG and SWD transports.
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32l5x
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}
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source [find target/stm32x5x_common.cfg]
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proc stm32l5x_clock_config {} {
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set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
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# MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
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# RCC_APB1ENR1 = PWREN
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mww [expr {0x40021058 + $offset}] 0x10000000
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# delay for register clock enable (read back reg)
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mrw [expr {0x40021058 + $offset}]
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# PWR_CR1 : VOS Range 0
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mww [expr {0x40007000 + $offset}] 0
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# while (PWR_SR2 & VOSF)
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while {([mrw [expr {0x40007014 + $offset}]] & 0x0400)} {}
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# FLASH_ACR : 5 WS for 110 MHz HCLK
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mww 0x40022000 0x00000005
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# RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz
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# fVCO = 4 x 55 /1 = 220
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# SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz
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mww [expr {0x4002100C + $offset}] 0x01003711
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# RCC_CR |= PLLON
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mmw [expr {0x40021000 + $offset}] 0x01000000 0
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# while !(RCC_CR & PLLRDY)
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while {!([mrw [expr {0x40021000 + $offset}]] & 0x02000000)} {}
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# RCC_CFGR |= SW_PLL
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mmw [expr {0x40021008 + $offset}] 0x00000003 0
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# while ((RCC_CFGR & SWS) != PLL)
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while {([mrw [expr {0x40021008 + $offset}]] & 0x0C) != 0x0C} {}
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}
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$_TARGETNAME configure -event reset-init {
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stm32l5x_clock_config
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# Boost JTAG frequency
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adapter speed 4000
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}
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