180 lines
5.3 KiB
INI
180 lines
5.3 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# TI/Luminary Stellaris LM3S chip family
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# Some devices have errata in returning their device class.
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# DEVICECLASS is provided as a manual override
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# Manual setting of a device class of 0xff is not allowed
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global _DEVICECLASS
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if { [info exists DEVICECLASS] } {
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set _DEVICECLASS $DEVICECLASS
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} else {
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set _DEVICECLASS 0xff
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}
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# Luminary chips support both JTAG and SWD transports.
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# Adapt based on what transport is active.
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source [find target/swj-dp.tcl]
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# For now we ignore the SPI and UART options, which
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# are usable only for ISP style initial flash programming.
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME lm3s
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}
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# CPU TAP ID 0x1ba00477 for early Sandstorm parts
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# CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
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# CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
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# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm)
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# CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard)
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# ... we'll ignore the JTAG version field, rather than list every
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# chip revision that turns up.
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x0ba00477
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}
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# SWD DAP, and JTAG TAP, take same params for now;
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# ... even though SWD ignores all except TAPID, and
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# JTAG shouldn't need anything more then irlen. (and TAPID).
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swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
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-expected-id $_CPUTAPID -ignore-version
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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# default to 2K working area
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set _WORKAREASIZE 0x800
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
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# 8K working area at base of ram, not backed up
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#
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# NOTE: you may need or want to reconfigure the work area;
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# some parts have just 6K, and you may want to use other
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# addresses (at end of mem not beginning) or back it up.
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
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# JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
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# LM3S parts don't support RTCK
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#
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# NOTE: this may be increased by a reset-init handler, after it
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# configures and enables the PLL. Or you might need to decrease
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# this, if you're using a slower clock.
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adapter speed 500
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source [find mem_helper.tcl]
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proc reset_peripherals {family} {
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source [find chip/ti/lm3s/lm3s.tcl]
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echo "Resetting Core Peripherals"
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# Disable the PLL and the system clock divider (nop if disabled)
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mmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV
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mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0
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# RCC and RCC2 to their reset values
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mww $SYSCTL_RCC [expr {0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS)}]
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mww $SYSCTL_RCC2 0x07806810
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mww $SYSCTL_RCC 0x078e3ad1
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# Reset the deep sleep clock configuration register
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mww $SYSCTL_DSLPCLKCFG 0x07800000
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# Reset the clock gating registers
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mww $SYSCTL_RCGC0 0x00000040
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mww $SYSCTL_RCGC1 0
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mww $SYSCTL_RCGC2 0
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mww $SYSCTL_SCGC0 0x00000040
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mww $SYSCTL_SCGC1 0
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mww $SYSCTL_SCGC2 0
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mww $SYSCTL_DCGC0 0x00000040
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mww $SYSCTL_DCGC1 0
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mww $SYSCTL_DCGC2 0
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# Reset the remaining SysCtl registers
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mww $SYSCTL_PBORCTL 0
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mww $SYSCTL_IMC 0
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mww $SYSCTL_GPIOHBCTL 0
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mww $SYSCTL_MOSCCTL 0
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mww $SYSCTL_PIOSCCAL 0
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mww $SYSCTL_I2SMCLKCFG 0
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# Reset the peripherals
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mww $SYSCTL_SRCR0 0xffffffff
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mww $SYSCTL_SRCR1 0xffffffff
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mww $SYSCTL_SRCR2 0xffffffff
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mww $SYSCTL_SRCR0 0
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mww $SYSCTL_SRCR1 0
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mww $SYSCTL_SRCR2 0
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# Clear any pending SysCtl interrupts
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mww $SYSCTL_MISC 0xffffffff
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# Wait for any pending flash operations to complete
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while {[expr {[mrw $FLASH_FMC] & 0xffff}] != 0} { sleep 1 }
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while {[expr {[mrw $FLASH_FMC2] & 0xffff}] != 0} { sleep 1 }
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# Reset the flash controller registers
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mww $FLASH_FMA 0
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mww $FLASH_FCIM 0
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mww $FLASH_FCMISC 0xffffffff
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mww $FLASH_FWBVAL 0
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}
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$_TARGETNAME configure -event reset-start {
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adapter speed 500
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#
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# When nRST is asserted on most Stellaris devices, it clears some of
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# the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
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# and OpenOCD depends on those TRMs. So we won't use SRST on those
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# chips. (Only power-on reset should affect debug state, beyond a
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# few specified bits; not the chip's nRST input, wired to SRST.)
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#
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# REVISIT current errata specs don't seem to cover this issue.
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# Do we have more details than this email?
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# https://lists.berlios.de/pipermail
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# /openocd-development/2008-August/003065.html
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#
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global _DEVICECLASS
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if {$_DEVICECLASS != 0xff} {
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set device_class $_DEVICECLASS
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} else {
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set device_class [expr {([mrw 0x400fe000] >> 16) & 0xff}]
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}
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if {$device_class == 0 || $device_class == 1 ||
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$device_class == 3 || $device_class == 5 || $device_class == 0xa} {
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if {![using_hla]} {
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# Sandstorm, Fury, DustDevil, Blizzard and Snowflake are able to use NVIC SYSRESETREQ
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cortex_m reset_config sysresetreq
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}
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} else {
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if {![using_hla]} {
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# Tempest and Firestorm default to using NVIC VECTRESET
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# peripherals will need resetting manually, see proc reset_peripherals
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cortex_m reset_config vectreset
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}
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# reset peripherals, based on code in
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# http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
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reset_peripherals $device_class
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}
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}
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# flash configuration ... autodetects sizes, autoprobed
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flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
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