132 lines
3.4 KiB
INI
132 lines
3.4 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# OMAP4460
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME omap4460
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}
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# Although the OMAP4430 supposedly has an ICEpick-D, only the
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# ICEpick-C router commands seem to work.
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# See http://processors.wiki.ti.com/index.php/ICEPICK
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source [find target/icepick.cfg]
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#
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# A9 DAP
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#
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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set _DAP_TAPID 0x3BA00477
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_DAP_TAPID -disable
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jtag configure $_CHIPNAME.cpu -event tap-enable \
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"icepick_c_tapenable $_CHIPNAME.jrc 9"
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#
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# M3 DAPs, one per core
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#
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if { [info exists M3_DAP_TAPID] } {
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set _M3_DAP_TAPID $M3_DAP_TAPID
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} else {
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set _M3_DAP_TAPID 0x4BA00477
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}
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jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_M3_DAP_TAPID -disable
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jtag configure $_CHIPNAME.m31 -event tap-enable \
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"icepick_c_tapenable $_CHIPNAME.jrc 5"
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jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_M3_DAP_TAPID -disable
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jtag configure $_CHIPNAME.m30 -event tap-enable \
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"icepick_c_tapenable $_CHIPNAME.jrc 4"
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#
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# ICEpick-D JRC (JTAG route controller)
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#
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if { [info exists JRC_TAPID] } {
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set _JRC_TAPID $JRC_TAPID
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} else {
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set _JRC_TAPID 0x2b94e02f
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set _JRC_TAPID2 0x1b85202f
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}
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# PandaBoard REV EA1 (PEAP platforms)
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if { [info exists JRC_TAPID2] } {
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set _JRC_TAPID2 $JRC_TAPID2
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} else {
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set _JRC_TAPID2 0x1b85202f
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}
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
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-expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2
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# Required by ICEpick to power-up the debug domain
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jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
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#
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# GDB target: Cortex-A9, using DAP
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#
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# The debugger can connect to either core of the A9, but currently
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# not both simultaneously. Change -coreid to 1 to connect to the
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# second core.
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#
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set _TARGETNAME $_CHIPNAME.cpu
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# APB DBGBASE reads 0x80040000, but this points to an empty ROM table.
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# 0x80000000 is cpu0 coresight region
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#
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#
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# CORTEX_A8_PADDRDBG_CPU_SHIFT 13
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# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)
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set _coreid 0
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set _dbgbase [expr {0x80000000 | ($_coreid << 13)}]
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echo "Using dbgbase = [format 0x%x $_dbgbase]"
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
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-coreid 0 -dbgbase $_dbgbase
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# SRAM: 56KiB at 0x4030.0000
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$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
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#
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# M3 targets, separate TAP/DAP for each core
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#
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dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
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dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
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target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
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target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
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# Once the JRC is up, enable our TAPs
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jtag configure $_CHIPNAME.jrc -event setup "
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jtag tapenable $_CHIPNAME.cpu
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jtag tapenable $_CHIPNAME.m30
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jtag tapenable $_CHIPNAME.m31
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"
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# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
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# ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset.
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set PRM_RSTCTRL 0x4A307B00
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$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"
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$_CHIPNAME.m30 configure -event reset-assert { }
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$_CHIPNAME.m31 configure -event reset-assert { }
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# Soft breakpoints don't currently work due to broken cache handling
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gdb breakpoint_override hard
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