58 lines
1.5 KiB
INI
58 lines
1.5 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# script for Nuvoton NPCX Cortex-M4 Series
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# Adapt based on what transport is active.
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source [find target/swj-dp.tcl]
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# Set Chipname
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME npcx
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}
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# SWD DAP ID of Nuvoton NPCX Cortex-M4.
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if { [info exists CPUDAPID ] } {
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set _CPUDAPID $CPUDAPID
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} else {
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set _CPUDAPID 0x4BA00477
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 32kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x8000
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}
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if { [info exists FIUNAME]} {
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set _FIUNAME $FIUNAME
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} else {
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set _FIUNAME npcx.fiu
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}
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# Debug Adapter Target Settings
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swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x200c0000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# Initial JTAG/SWD speed
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# For safety purposes, set for the lowest cpu clock configuration
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# 4MHz / 6 = 666KHz, so use 600KHz for it
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adapter speed 600
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# For safety purposes, set for the lowest cpu clock configuration
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$_TARGETNAME configure -event reset-start {adapter speed 600}
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# use sysresetreq to perform a system reset
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cortex_m reset_config sysresetreq
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# flash configuration
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME $_FIUNAME
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