71 lines
1.8 KiB
INI
71 lines
1.8 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# imx31 config
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#
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reset_config trst_and_srst srst_gates_jtag
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adapter srst delay 5
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME imx31
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x07b3601d
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}
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if { [info exists SDMATAPID] } {
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set _SDMATAPID $SDMATAPID
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} else {
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set _SDMATAPID 0x2190101d
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}
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if { [info exists ETBTAPID] } {
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set _ETBTAPID $ETBTAPID
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} else {
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set _ETBTAPID 0x2b900f0f
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}
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#========================================
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jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
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# The "SDMA" - <S>mart <DMA> controller debug tap
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# Based on some IO pins - this can be disabled & removed
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# See diagram: 6-14
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# SIGNAL NAME:
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# SJC_MOD - controls multiplexer - disables ARM1136
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# SDMA_BYPASS - disables SDMA -
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#
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# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
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jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
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# No IDCODE for this TAP
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jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0
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# Per section 40.17.1, table 40-85 the IR register is 4 bits
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# But this conflicts with Diagram 6-13, "3bits ir and drs"
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jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
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proc power_restore {} { echo "Sensed power restore. No action." }
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proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
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# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
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etm config $_TARGETNAME 16 normal full etb
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etb config $_TARGETNAME $_CHIPNAME.etb
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