98 lines
3.7 KiB
INI
98 lines
3.7 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# Thanks to Pieter Conradie for this script!
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#
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# Unknown vendor board contains:
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#
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# Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz
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# OSCSEL configured for internal RC oscillator (22 to 42 kHz)
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#
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# 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit
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# 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks
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##################################################################
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# We add to the minimal configuration.
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source [find target/at91sam9260.cfg]
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$_TARGETNAME configure -event reset-start {
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# At reset CPU runs at 22 to 42 kHz.
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# JTAG Frequency must be 6 times slower.
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jtag_rclk 3
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halt
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# RSTC_MR : enable user reset, MMU may be enabled... use physical address
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mww phys 0xfffffd08 0xa5000501
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}
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$_TARGETNAME configure -event reset-init {
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mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
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mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
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sleep 20 ;# wait 20 ms
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mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
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sleep 10 ;# wait 10 ms
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mww 0xfffffc28 0x205dbf09 ;# CKGR_PLLAR: Set PLLA Register for 192.512MHz
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sleep 20 ;# wait 20 ms
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mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2)
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sleep 10 ;# wait 10 ms
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mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected (96.256 MHz)
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sleep 10 ;# wait 10 ms
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# Increase JTAG Speed to 6 MHz if RCLK is not supported
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jtag_rclk 6000
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arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
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mww 0xffffec00 0x01020102 ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
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mww 0xffffec04 0x09070806 ;# SMC_PULSE0
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mww 0xffffec08 0x000d000b ;# SMC_CYCLE0
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mww 0xffffec0c 0x00001003 ;# SMC_MODE0
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flash probe 0 ;# Identify flash bank 0
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mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
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mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
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mww 0xfffff860 0xffff0000 ;# PIO_PUDR : Disable D15..D31 pull-ups
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mww 0xffffef1c 0x00010102 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
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# VDDIOMSEL set for +3V3 memory
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# Disable D0..D15 pull-ups
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mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
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mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
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mww 0x20000000 0
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mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
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mww 0x20000000 0
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mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
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mww 0x20000000 0
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mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
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mww 0x20000000 0
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mww 0xffffea04 0x2a2 ;# SDRAMC_TR : Set refresh timer count to 7us
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}
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#####################
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# Flash configuration
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#####################
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#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
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