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riscv-openocd/tcl/board/mini2440.cfg

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# SPDX-License-Identifier: GPL-2.0-or-later
#-------------------------------------------------------------------------
# Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R
# NOTE: Configured for NAND boot (switch S2 in NANDBOOT)
# 64 MB NAND (Samsung K9D1208V0M)
# B Findlay 08/09
#
# ----------- Important notes to help you on your way ----------
# README:
# NOR/NAND Boot Switch - I have not read the vivi source, but from
# what I could tell from reading the registers it appears that vivi
# loads itself into DRAM and then flips NFCONT (0x4E000004) bits
# Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND
# FLASH at the bottom 64MB of memory. This essentially takes the
# NOR Flash out of the circuit so you can't trash it.
#
# I adapted the samsung_s3c2440.cfg file which is why I did not
# include "source [find target/samsung_s3c2440.cfg]". I believe
# the -work-area-phys 0x200000 is incorrect, but also had to pad
# some additional resets. I didn't modify it as if it is working
# for someone, the work-area-phys is not used by most.
#
# JTAG ADAPTER SPECIFIC
# IMPORTANT! Any JTAG device that uses ADAPTIVE CLOCKING will likely
# FAIL as the pin RTCK on the mini2440 10 pin JTAG Conn doesn't exist.
# This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is
# necessary to FORCE setting the clock. Normally this should be configured
# in the openocd.cfg file, but was placed here as it can be a tough
# problem to figure out. THIS MAY NOT FIX YOUR PROBLEM.. I modified
# the openOCD driver jlink.c and posted it here. It may eventually end
# up changed in openOCD, but its a hack in the driver and really should
# be in the jtag layer (core.c me thinks), but haven't done it yet. My
# hack for jlink.c may be found here.
#
# http://forum.sparkfun.com/viewtopic.php?t=16763&sid=946e65abdd3bab39cc7d90dee33ff135
#
# Note: Also if you have a USB JTAG, you will need the USB library installed
# on your system "libusb-dev" or the make of openocd will fail. I *think*
# it's apt-get install libusb-dev. When I made my config I only included
# --enable-jlink and --enable-usbdevs
#
# I HAVE NOT Tested this thoroughly, so there could still be problems.
# But it should get you way ahead of the game from where I started.
# If you find problems (and fixes) please post them to
# openocd-development@lists.berlios.de and join the developers and
# check in fixes to this and anything else you find. I do not
# provide support, but if you ask really nice and I see anything
# obvious I will tell you.. mostly just dig, fix, and submit to openocd.
#
# best! brfindla@yahoo.com Nashua, NH USA
#
# Recommended resources:
# - first two are the best Mini2440 resources anywhere
# - maintained by buserror... thanks guy!
#
# http://bliterness.blogspot.com/
# http://code.google.com/p/mini2440/
#
# others....
#
# http://forum.sparkfun.com/viewforum.php?f=18
# http://labs.kernelconcepts.de/Publications/Micro24401/
# http://www.friendlyarm.net/home
# http://www.amontec.com/jtag_pinout.shtml
#
#-------------------------------------------------------------------------
#
#
# Your openocd.cfg file should contain:
# source [find interface/<yourjtag>.cfg]
# source [find board/mini2440.cfg]
#
#
#
# FIXME use some standard target config, maybe create one from this
#
# source [find target/...cfg]
#-------------------------------------------------------------------------
# Target configuration for the Samsung 2440 system on chip
# Tested on a S3C2440 Evaluation board by keesj
# Processor : ARM920Tid(wb) rev 0 (v4l)
# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d
# (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
#-------------------------------------------------------------------------
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME s3c2440
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
# this defaults to a bigendian
set _ENDIAN little
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x0032409d
}
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 1
#reset configuration
adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
#-------------------------------------------------------------------------
# JTAG ADAPTER SPECIFIC
# IMPORTANT! See README at top of this file.
#-------------------------------------------------------------------------
adapter speed 12000
#-------------------------------------------------------------------------
# GDB Setup
#-------------------------------------------------------------------------
gdb breakpoint_override hard
#------------------------------------------------
# ARM SPECIFIC
#------------------------------------------------
targets
# arm7_9 dcc_downloads enable
# arm7_9 fast_memory_access enable
nand device s3c2440 0
adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
init
echo " "
echo "-------------------------------------------"
echo "--- login with - telnet localhost 4444 ---"
echo "--- then type help_2440 ---"
echo "-------------------------------------------"
echo " "
#------------------------------------------------
# Processor Initialialization
# Note: Processor writes can only occur when
# the state is in SYSTEM. When you call init_2440
# one of the first lines will tell you what state
# you are in. If a linux image is booting
# when you run this, it will not work
# a vivi boot loader will run with this just
# fine. The reg values were obtained by a combination
# of figuring them out fromt the manual, and looking
# at post vivi values with the debugger. Don't
# place too much faith in them, but seem to work.
#------------------------------------------------
proc init_2440 { } {
halt
s3c2440.cpu curstate
#-----------------------------------------------
# Set Processor Clocks - mini2440 xtal=12mHz
# we set main clock for 405mHZ
# we set the USB Clock for 48mHz
# OM2 OM3 pulled to ground so main clock and
# usb clock are off 12mHz xtal
#-----------------------------------------------
mww phys 0x4C000014 0x00000005 ;# Clock Divider control Reg
mww phys 0x4C000000 0xFFFFFFFF ;# LOCKTIME count register
mww phys 0x4C000008 0x00038022 ;# UPPLCON USB clock config Reg
mww phys 0x4C000004 0x0007F021 ;# MPPLCON Proc clock config Reg
#-----------------------------------------------
# Configure Memory controller
# BWSCON configures all banks, NAND, NOR, DRAM
# DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
#-----------------------------------------------
mww phys 0x48000000 0x22111112 ;# BWSCON - Bank and Bus Width
mww phys 0x48000010 0x00001112 ;# BANKCON4 - ?
mww phys 0x4800001c 0x00018009 ;# BANKCON6 - DRAM
mww phys 0x48000020 0x00018009 ;# BANKCON7 - DRAM
mww phys 0x48000024 0x008E04EB ;# REFRESH - DRAM
mww phys 0x48000028 0x000000B2 ;# BANKSIZE - DRAM
mww phys 0x4800002C 0x00000030 ;# MRSRB6 - DRAM
mww phys 0x48000030 0x00000030 ;# MRSRB7 - DRAM
#-----------------------------------------------
# Now port configuration for enables for memory
# and other stuff.
#-----------------------------------------------
mww phys 0x56000000 0x007FFFFF ;# GPACON
mww phys 0x56000010 0x00295559 ;# GPBCON
mww phys 0x56000018 0x000003FF ;# GPBUP (PULLUP ENABLE)
mww phys 0x56000014 0x000007C2 ;# GPBDAT
mww phys 0x56000020 0xAAAAA6AA ;# GPCCON
mww phys 0x56000028 0x0000FFFF ;# GPCUP
mww phys 0x56000024 0x00000020 ;# GPCDAT
mww phys 0x56000030 0xAAAAAAAA ;# GPDCON
mww phys 0x56000038 0x0000FFFF ;# GPDUP
mww phys 0x56000040 0xAAAAAAAA ;# GPECON
mww phys 0x56000048 0x0000FFFF ;# GPEUP
mww phys 0x56000050 0x00001555 ;# GPFCON
mww phys 0x56000058 0x0000007F ;# GPFUP
mww phys 0x56000054 0x00000000 ;# GPFDAT
mww phys 0x56000060 0x00150114 ;# GPGCON
mww phys 0x56000068 0x0000007F ;# GPGUP
mww phys 0x56000070 0x0015AAAA ;# GPHCON
mww phys 0x56000078 0x000003FF ;# GPGUP
}
proc flash_config { } {
#-----------------------------------------
# Finish Flash Configuration
#-----------------------------------------
halt
#flash configuration (K9D1208V0M: 512Mbit, x8, 3.3V, Mode: Normal, 1st gen)
nand probe 0
nand list
}
proc flash_uboot { } {
# flash the u-Boot binary and reboot into it
init_2440
flash_config
nand erase 0 0x0 0x40000
nand write 0 /tftpboot/u-boot-nand512.bin 0 oob_softecc_kw
resume
}
proc load_uboot { } {
echo " "
echo " "
echo "----------------------------------------------------------"
echo "---- Load U-Boot into RAM and execute it. ---"
echo "---- NOTE: loads, partially runs, and hangs ---"
echo "---- U-Boot is fine, this image runs from vivi. ---"
echo "---- I burned u-boot into NAND so I didn't finish ---"
echo "---- debugging it. I am leaving this here as it is ---"
echo "---- part of the way there if you want to fix it. ---"
echo "---- ---"
echo "---- mini2440 U-boot here: ---"
echo "---- http://repo.or.cz/w/u-boot-openmoko/mini2440.git ---"
echo "---- Also this: ---"
echo "---- http://code.google.com/p/mini2440/wiki/MiniBringup --"
echo "----------------------------------------------------------"
init_2440
echo "Loading /tftpboot/u-boot-nand512.bin"
load_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin
echo "Verifying image...."
verify_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin
echo "jumping to u-boot"
#bp 0x33f80068 4 hw
reg 0 0
reg 1 0
reg 2 0
reg 3 0
reg 4 0x33f80000
resume 0x33f80000
}
# this may help a little bit debugging the load_uboot
proc s {} {
step
reg
arm disassemble 0x33F80068 0x10
}
proc help_2440 {} {
echo " "
echo " "
echo "-----------------------------------------------------------"
echo "---- The following mini2440 funcs are supported ----"
echo "---- init_2440 - initialize clocks, DRAM, IO ----"
echo "---- flash_config - configures nand flash ----"
echo "---- load_uboot - loads uboot into ram ----"
echo "---- flash_uboot - flashes uboot to nand (untested) ----"
echo "---- help_2440 - this help display ----"
echo "-----------------------------------------------------------"
echo " "
echo " "
}
#----------------------------------------------------------------------------
#----------------------------------- END ------------------------------------
#----------------------------------------------------------------------------
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