102 lines
2.0 KiB
INI
102 lines
2.0 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# The IMX31PDK eval board has a single IMX31 chip
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source [find target/imx31.cfg]
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source [find target/imx.cfg]
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$_TARGETNAME configure -event reset-init { imx31pdk_init }
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proc self_test {} {
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echo "Running 100 iterations of test."
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dump_image /ram/test 0x80000000 0x40000
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for {set i 0} {$i < 100} {set i [expr {$i+1}]} {
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echo "Iteration $i"
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reset init
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mww 0x80000000 0x12345678 0x10000
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load_image /ram/test 0x80000000 bin
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verify_image /ram/test 0x80000000 bin
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}
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}
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# Slow fallback frequency
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# measure_clk indicates ca. 3-4MHz.
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jtag_rclk 1000
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proc imx31pdk_init { } {
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imx3x_reset
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# This setup puts RAM at 0x80000000
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mww 0x53FC0000 0x040
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mww 0x53F80000 0x074B0B7D
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# 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
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#mww 0x53F80004 0xFF871D50
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#mww 0x53F80010 0x00271C1B
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# Start 16 bit NorFlash Initialization on CS0
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mww 0xb8002000 0x0000CC03
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mww 0xb8002004 0xa0330D01
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mww 0xb8002008 0x00220800
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# Configure CPLD on CS4
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mww 0xb8002040 0x0000DCF6
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mww 0xb8002044 0x444A4541
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mww 0xb8002048 0x44443302
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# SDCLK
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mww 0x43FAC26C 0
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# CAS
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mww 0x43FAC270 0
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# RAS
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mww 0x43FAC274 0
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# CS2 (CSD0)
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mww 0x43FAC27C 0x1000
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# DQM3
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mww 0x43FAC284 0
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# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
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mww 0x43FAC288 0
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mww 0x43FAC28C 0
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mww 0x43FAC290 0
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mww 0x43FAC294 0
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mww 0x43FAC298 0
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mww 0x43FAC29C 0
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mww 0x43FAC2A0 0
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mww 0x43FAC2A4 0
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mww 0x43FAC2A8 0
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mww 0x43FAC2AC 0
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mww 0x43FAC2B0 0
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mww 0x43FAC2B4 0
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mww 0x43FAC2B8 0
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mww 0x43FAC2BC 0
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mww 0x43FAC2C0 0
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mww 0x43FAC2C4 0
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mww 0x43FAC2C8 0
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mww 0x43FAC2CC 0
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mww 0x43FAC2D0 0
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mww 0x43FAC2D4 0
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mww 0x43FAC2D8 0
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mww 0x43FAC2DC 0
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# Initialization script for 32 bit DDR on MX31 ADS
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mww 0xB8001010 0x00000004
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mww 0xB8001004 0x006ac73a
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mww 0xB8001000 0x92100000
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mww 0x80000f00 0x12344321
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mww 0xB8001000 0xa2100000
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mww 0x80000000 0x12344321
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mww 0x80000000 0x12344321
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mww 0xB8001000 0xb2100000
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mwb 0x80000033 0xda
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mwb 0x81000000 0xff
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mww 0xB8001000 0x82226080
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mww 0x80000000 0xDEADBEEF
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mww 0xB8001010 0x0000000c
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}
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