451 lines
16 KiB
Tcl
451 lines
16 KiB
Tcl
# SPDX-License-Identifier: GPL-2.0-or-later
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#################################################################################################
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# Author: Benjamin Tietz <benjamin.tietz@in-circuit.de> ;#
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# based on work from: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> ;#
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# Kiwigrid GmbH ;#
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# Generated for In-Circuit i.MX53 SO-Dimm ;#
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#################################################################################################
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# The In-Circuit ICnova IMX53SODIMM board has a single IMX53 chip
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source [find target/imx53.cfg]
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# Helper for common memory read/modify/write procedures
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source [find mem_helper.tcl]
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echo "i.MX53 SO-Dimm board lodaded."
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# Set reset type
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#reset_config srst_only
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adapter speed 3000
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# Slow speed to be sure it will work
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jtag_rclk 1000
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$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
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$_TARGETNAME configure -event "reset-assert" {
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echo "Resetting ...."
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#cortex_a dbginit
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}
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$_TARGETNAME configure -event reset-init { sodimm_init }
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global AIPS1_BASE_ADDR
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set AIPS1_BASE_ADDR 0x53F00000
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global AIPS2_BASE_ADDR
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set AIPS2_BASE_ADDR 0x63F00000
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proc sodimm_init { } {
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echo "Reset-init..."
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; # halt the CPU
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halt
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echo "HW version [format %x [mrw 0x48]]"
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dap apsel 1
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DCD
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; # ARM errata ID #468414
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set tR [arm mrc 15 0 1 0 1]
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arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit
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init_l2cc
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init_aips
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init_clock
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dap apsel 0
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; # Force ARM state
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; #reg cpsr 0x000001D3
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arm core_state arm
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jtag_rclk 3000
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# adapter speed 3000
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}
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# L2CC Cache setup/invalidation/disable
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proc init_l2cc { } {
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; #/* explicitly disable L2 cache */
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; #mrc 15, 0, r0, c1, c0, 1
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set tR [arm mrc 15 0 1 0 1]
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; #bic r0, r0, #0x2
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; #mcr 15, 0, r0, c1, c0, 1
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arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
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; #/* reconfigure L2 cache aux control reg */
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; #mov r0, #0xC0 /* tag RAM */
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; #add r0, r0, #0x4 /* data RAM */
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; #orr r0, r0, #(1 << 24) /* disable write allocate delay */
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; #orr r0, r0, #(1 << 23) /* disable write allocate combine */
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; #orr r0, r0, #(1 << 22) /* disable write allocate */
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; #mcr 15, 1, r0, c9, c0, 2
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arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
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}
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# AIPS setup - Only setup MPROTx registers.
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# The PACR default values are good.
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proc init_aips { } {
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; # Set all MPROTx to be non-bufferable, trusted for R/W,
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; # not forced to user-mode.
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global AIPS1_BASE_ADDR
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global AIPS2_BASE_ADDR
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set VAL 0x77777777
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# dap apsel 1
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mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
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mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
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mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
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mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
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# dap apsel 0
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}
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proc init_clock { } {
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global AIPS1_BASE_ADDR
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global AIPS2_BASE_ADDR
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set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}]
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set CLKCTL_CCSR 0x0C
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set CLKCTL_CBCDR 0x14
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set CLKCTL_CBCMR 0x18
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set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}]
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set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}]
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set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}]
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set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}]
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set CLKCTL_CSCMR1 0x1C
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set CLKCTL_CDHIPR 0x48
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set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}]
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set CLKCTL_CSCDR1 0x24
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set CLKCTL_CCDR 0x04
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; # Switch ARM to step clock
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
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return
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echo "not returned"
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setup_pll $PLL1_BASE_ADDR 800
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setup_pll $PLL3_BASE_ADDR 400
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; # Switch peripheral to PLL3
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
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while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
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setup_pll $PLL2_BASE_ADDR 400
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; # Switch peripheral to PLL2
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
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; # change uart clk parent to pll2
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
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; # make sure change is effective
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while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
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setup_pll $PLL3_BASE_ADDR 216
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setup_pll $PLL4_BASE_ADDR 455
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; # Set the platform clock dividers
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mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
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mww [expr {$CCM_BASE_ADDR + 0x10}] 0
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; # Switch ARM back to PLL 1.
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
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; # make uart div=6
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
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; # Restore the default values in the Gate registers
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mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
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; # for cko - for ARM div by 8
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mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
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}
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proc setup_pll { PLL_ADDR CLK } {
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set PLL_DP_CTL 0x00
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set PLL_DP_CONFIG 0x04
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set PLL_DP_OP 0x08
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set PLL_DP_HFS_OP 0x1C
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set PLL_DP_MFD 0x0C
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set PLL_DP_HFS_MFD 0x20
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set PLL_DP_MFN 0x10
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set PLL_DP_HFS_MFN 0x24
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if {$CLK == 1000} {
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set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}]
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set DP_MFD [expr {12 - 1}]
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set DP_MFN 5
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} elseif {$CLK == 850} {
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set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
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set DP_MFD [expr {48 - 1}]
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set DP_MFN 41
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} elseif {$CLK == 800} {
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set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
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set DP_MFD [expr {3 - 1}]
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set DP_MFN 1
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} elseif {$CLK == 700} {
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set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}]
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set DP_MFD [expr {24 - 1}]
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set DP_MFN 7
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} elseif {$CLK == 600} {
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set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
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set DP_MFD [expr {4 - 1}]
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set DP_MFN 1
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} elseif {$CLK == 665} {
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set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
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set DP_MFD [expr {96 - 1}]
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set DP_MFN 89
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} elseif {$CLK == 532} {
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set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}]
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set DP_MFD [expr {24 - 1}]
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set DP_MFN 13
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} elseif {$CLK == 455} {
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set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
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set DP_MFD [expr {48 - 1}]
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set DP_MFN 71
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} elseif {$CLK == 400} {
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set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
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set DP_MFD [expr {3 - 1}]
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set DP_MFN 1
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} elseif {$CLK == 216} {
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set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}]
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set DP_MFD [expr {4 - 1}]
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set DP_MFN 3
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} else {
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error "Error (setup_dll): clock not found!"
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}
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mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
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mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
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mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
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mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
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mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
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mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
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mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
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mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
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mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
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while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
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}
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proc CPU_2_BE_32 { L } {
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return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}]
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}
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# Device Configuration Data
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proc DCD { } {
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# dap apsel 1
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#*========================================================================================== ======
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# Initialization script for 32 bit DDR3 (CS0+CS1)
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#*========================================================================================== ======
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# Remux D24/D25 to perform Flash-access
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mww 0x53fa818C 0x00000000 ; #EIM_RW
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mww 0x53fa8180 0x00000000 ; #EIM_CS0
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mww 0x53fa8188 0x00000000 ; #EIM_OE
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mww 0x53fa817C 0x00000000 ; #A16
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mww 0x53fa8178 0x00000000 ; #A17
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mww 0x53fa8174 0x00000000 ; #A18
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mww 0x53fa8170 0x00000000 ; #A19
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mww 0x53fa816C 0x00000000 ; #A20
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mww 0x53fa8168 0x00000000 ; #A21
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mww 0x53fa819C 0x00000000 ; #DA0
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mww 0x53fa81A0 0x00000000 ; #DA1
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mww 0x53fa81A4 0x00000000 ; #DA2
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mww 0x53fa81A8 0x00000000 ; #DA3
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mww 0x53fa81AC 0x00000000 ; #DA4
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mww 0x53fa81B0 0x00000000 ; #DA5
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mww 0x53fa81B4 0x00000000 ; #DA6
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mww 0x53fa81B8 0x00000000 ; #DA7
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mww 0x53fa81BC 0x00000000 ; #DA8
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mww 0x53fa81C0 0x00000000 ; #DA9
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mww 0x53fa81C4 0x00000000 ; #DA10
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mww 0x53fa81C8 0x00000000 ; #DA11
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mww 0x53fa81CC 0x00000000 ; #DA12
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mww 0x53fa81D0 0x00000000 ; #DA13
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mww 0x53fa81D4 0x00000000 ; #DA14
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mww 0x53fa81D8 0x00000000 ; #DA15
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mww 0x53fa8118 0x00000000 ; #D16
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mww 0x53fa811C 0x00000000 ; #D17
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mww 0x53fa8120 0x00000000 ; #D18
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mww 0x53fa8124 0x00000000 ; #D19
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mww 0x53fa8128 0x00000000 ; #D20
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mww 0x53fa812C 0x00000000 ; #D21
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mww 0x53fa8130 0x00000000 ; #D22
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mww 0x53fa8134 0x00000000 ; #D23
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mww 0x53fa813c 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D24
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mww 0x53fa8140 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D25
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mww 0x53fa8144 0x00000000 ; #D26
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mww 0x53fa8148 0x00000000 ; #D27
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mww 0x53fa814C 0x00000000 ; #D28
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mww 0x53fa8150 0x00000000 ; #D29
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mww 0x53fa8154 0x00000000 ; #D30
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mww 0x53fa8158 0x00000000 ; #D31
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# DDR3 IOMUX configuration
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#* Global pad control options */
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mww 0x53fa8554 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
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mww 0x53fa8558 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
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mww 0x53fa8560 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
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mww 0x53fa8564 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
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mww 0x53fa8568 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
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mww 0x53fa8570 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - boazp: weaker sdclk EVK DDR max frequency
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mww 0x53fa8574 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
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mww 0x53fa8578 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - boazp: weaker sdclk EVK DDR max frequency
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mww 0x53fa857c 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
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mww 0x53fa8580 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
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mww 0x53fa8584 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
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mww 0x53fa8588 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
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mww 0x53fa8590 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
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mww 0x53fa8594 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
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mww 0x53fa86f0 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_ADDDS
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mww 0x53fa86f4 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
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mww 0x53fa86fc 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRPKE
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# mww 0x53fa8714 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
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mww 0x53fa8714 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
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mww 0x53fa8718 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B0DS
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mww 0x53fa871c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B1DS
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mww 0x53fa8720 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_CTLDS
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mww 0x53fa8724 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=0 XXX
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mww 0x53fa8728 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B2DS
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mww 0x53fa872c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B3DS
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# mww 0x53fa86f4 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL for sDQS[3:0], 1=DDR2, 0=CMOS mode
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# mww 0x53fa8714 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE for D[31:0], 1=DDR2, 0=CMOS mode
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# mww 0x53fa86fc 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRPKE
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# mww 0x53fa8724 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=00
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#* Data bus byte lane pad drive strength control options */
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# mww 0x53fa872c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B3DS
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# mww 0x53fa8554 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
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# mww 0x53fa8558 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
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# mww 0x53fa8728 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B2DS
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# mww 0x53fa8560 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
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# mww 0x53fa8568 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
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# mww 0x53fa871c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B1DS
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# mww 0x53fa8594 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
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# mww 0x53fa8590 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
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# mww 0x53fa8718 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B0DS
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# mww 0x53fa8584 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
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# mww 0x53fa857c 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
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#* SDCLK pad drive strength control options */
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# mww 0x53fa8578 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
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# mww 0x53fa8570 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
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#* Control and addr bus pad drive strength control options */
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# mww 0x53fa8574 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
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# mww 0x53fa8588 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
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# mww 0x53fa86f0 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_ADDDS for DDR addr bus
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# mww 0x53fa8720 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_CTLDS for CSD0, CSD1, SDCKE0, SDCKE1, SDWE
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# mww 0x53fa8564 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
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# mww 0x53fa8580 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
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# Initialize DDR3 memory - Micron MT41J128M16-187Er
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#** Keep for now, same setting as CPU3 board **#
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mww 0x63fd901c 0x00008000
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# mww 0x63fd904c 0x01680172 ; #write leveling reg 0
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# mww 0x63fd9050 0x0021017f ; #write leveling reg 1
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mww 0x63fd9088 0x32383535 ; #read delay lines
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mww 0x63fd9090 0x40383538 ; #write delay lines
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# mww 0x63fd90F8 0x00000800 ; #Measure unit
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mww 0x63fd907c 0x0136014d ; #DQS gating 0
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mww 0x63fd9080 0x01510141 ; #DQS gating 1
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#* CPU3 Board settingr
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# Enable bank interleaving, Address mirror on, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
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# mww 0x63fd9018 0x00091740 ; #Misc register:
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#* Quick Silver board setting
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# Enable bank interleaving, Address mirror off, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
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mww 0x63fd9018 0x00011740 ; #Misc register
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# Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
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# mww 0x63fd9000 0xc3190000 ; #Main control register
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# Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
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mww 0x63fd9000 0x83190000 ; #Main control register
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# tRFC=64ck;tXS=68;tXP=3;tXPDLL=10;tFAW=15;CAS=6ck
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mww 0x63fd900C 0x555952E3 ; #timing configuration Reg 0
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# tRCD=6;tRP=6;tRC=21;tRAS=15;tRPA=1;tWR=6;tMRD=4;tCWL=5ck
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mww 0x63fd9010 0xb68e8b63 ; #timing configuration Reg 1
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# tDLLK(tXSRD)=512 cycles; tRTP=4;tWTR=4;tRRD=4
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mww 0x63fd9014 0x01ff00db ; #timing configuration Reg 2
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mww 0x63fd902c 0x000026d2 ; #command delay (default)
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mww 0x63fd9030 0x009f0e21 ; #out of reset delays
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# Keep tAOFPD, tAONPD, tANPD, and tAXPD as default since they are bigger than calc values
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mww 0x63fd9008 0x12273030 ; #ODT timings
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# tCKE=3; tCKSRX=5; tCKSRE=5
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mww 0x63fd9004 0x0002002d
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#Power down control
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#**********************************
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#DDR device configuration:
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#**********************************
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#**********************************
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# CS0:
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#**********************************
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mww 0x63fd901c 0x00008032 ; #write mode reg MR2 with cs0 (see below for settings)
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# Full array self refresh
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# Rtt_WR disabled (no ODT at IO CMOS operation)
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# Manual self refresh
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# CWS=5
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mww 0x63fd901c 0x00008033 ; #write mode reg MR3 with cs0.
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mww 0x63fd901c 0x00028031 ; #write mode reg MR1 with cs0. ODS=01: out buff= RZQ/7 (see below for settings)
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# out impedance = RZQ/7
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# Rtt_nom disabled (no ODT at IO CMOS operation)
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# Aditive latency off
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# write leveling disabled
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# tdqs (differential?) disabled
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mww 0x63fd901c 0x09208030 ; #write mode reg MR0 with cs0 , with dll_rst0
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mww 0x63fd901c 0x04008040 ; #ZQ calibration with cs0 (A10 high indicates ZQ cal long ZQCL)
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#**********************************
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# CS1:
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#**********************************
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# mww 0x63fd901c 0x0000803a ; #write mode reg MR2 with cs1.
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# mww 0x63fd901c 0x0000803b ; #write mode reg MR3 with cs1.
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# mww 0x63fd901c 0x00028039 ; #write mode reg MR1 with cs1. ODS=01: out buff= RZQ/7
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# mww 0x63fd901c 0x09208138 ; #write mode reg MR0 with cs1.
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# mww 0x63fd901c 0x04008048 ; #ZQ calibration with cs1(A10 high indicates ZQ cal long ZQCL)
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#**********************************
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mww 0x63fd9020 0x00001800 ; # Refresh control register
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mww 0x63fd9040 0x04b80003 ; # ZQ HW control
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mww 0x63fd9058 0x00022227 ; # ODT control register
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mww 0x63fd901c 0x00000000
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# CLKO muxing (comment out for now till needed to avoid conflicts with intended usage of signals)
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# mww 0x53FA8314 = 0
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# mww 0x53FA8320 0x4
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# mww 0x53FD4060 0x01e900f0
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|
|
# dap apsel 0
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}
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# IRAM
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$_TARGETNAME configure -work-area-phys 0xF8000000 -work-area-size 0x20000 -work-area-backup 1
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flash bank mx535_nor cfi 0xf0000000 0x800000 2 2 $_TARGETNAME
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# vim:filetype=tcl
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