74 lines
1.4 KiB
INI
74 lines
1.4 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# The Cogent CSB732 board has a single i.MX35 chip
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source [find target/imx35.cfg]
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# Determined by trial and error
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reset_config trst_and_srst combined
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adapter srst delay 200
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jtag_ntrst_delay 200
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$_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-init { csb732_init }
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# Bare-bones initialization of core clocks and SDRAM
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proc csb732_init { } {
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# Disable fast writing only for init
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memwrite burst disable
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# All delay loops are omitted.
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# We assume the interpreter latency is enough.
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# Allow access to all coprocessors
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arm mcr 15 0 15 1 0 0x2001
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# Disable MMU, caches, write buffer
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arm mcr 15 0 1 0 0 0x78
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# Grant manager access to all domains
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arm mcr 15 0 3 0 0 0xFFFFFFFF
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# Set ARM clock to 532 MHz, AHB to 133 MHz
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mww 0x53F80004 0x1000
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# Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
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mww 0x53F8001C 0xB2C01
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set ESDMISC 0xB8001010
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set ESDCFG0 0xB8001004
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set ESDCTL0 0xB8001000
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# Enable DDR
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mww $ESDMISC 0x4
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# Timing
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mww $ESDCFG0 0x007fff3f
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# CS0
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mww $ESDCTL0 0x92120080
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# Precharge all dummy write
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mww 0x80000400 0
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# Enable CS) auto-refresh
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mww $ESDCTL0 0xA2120080
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# Refresh twice (dummy writes)
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mww 0x80000000 0
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mww 0x80000000 0
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# Enable CS0 load mode register
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mww $ESDCTL0 0xB2120080
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# Dummy writes
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mwb 0x80000033 0x01
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mwb 0x81000000 0x01
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mww $ESDCTL0 0x82226080
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mww 0x80000000 0
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# Re-enable fast writing
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memwrite burst enable
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}
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