173 lines
7.2 KiB
INI
173 lines
7.2 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# CALAO Systems USB-A9G20-C01
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# Authors: Gregory Hermant, Jean-Christophe PLAGNIOL-VILLARD, Wolfram Sang
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adapter driver ftdi
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ftdi device_desc "USB-A9G20"
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ftdi vid_pid 0x0403 0x6010
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ftdi layout_init 0x0c08 0x0f1b
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ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
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ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
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transport select jtag
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source [find target/at91sam9g20.cfg]
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source [find mem_helper.tcl]
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proc at91sam9g20_reset_start { } {
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# Make sure that the jtag is running slow, since there are a number of different ways the board
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# can be configured coming into this state that can cause communication problems with the jtag
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# adapter. Also since this call can be made following a "reset init" where fast memory accesses
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# are enabled, Need to temporarily shut this down so that the RSTC_MR register can be written at slower
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# jtag speed without causing GDB keep alive problem.
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arm7_9 fast_memory_access disable
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adapter speed 2 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
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halt 0 ;# Make sure processor is halted, or error will result in following steps.
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wait_halt 10000
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# RSTC_MR : enable user reset, MMU may be enabled... use physical address
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mww phys 0xfffffd08 0xa5000501
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}
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proc at91sam9g20_reset_init { } {
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# At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires
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# a number of steps that must be carefully performed. The process outline below follows the
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# recommended procedure outlined in the AT91SAM9G20 technical manual.
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#
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# Several key and very important things to keep in mind:
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# The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts. This
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# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
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# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
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mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog.
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# Set oscillator bypass bit (12.00 MHz external oscillator) in CKGR_MOR register.
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mww 0xfffffc20 0x00000002
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# Set PLLA Register for 798.000 MHz (divider: bypass, multiplier: 132).
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# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
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mww 0xfffffc28 0x20843F02
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while { [expr { [mrw 0xfffffc68] & 0x02 } ] != 2 } { sleep 1 }
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# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
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# Wait for MCKRDY signal from PMC_SR to assert.
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mww 0xfffffc30 0x00001300
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while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 }
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# Now change PMC_MCKR register to select PLLA.
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# Wait for MCKRDY signal from PMC_SR to assert.
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mww 0xfffffc30 0x00001302
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while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 }
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# Processor and master clocks are now operating and stable at maximum frequency possible:
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# -> MCLK = 133.000 MHz
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# -> PCLK = 400.000 MHz
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# Switch to fast JTAG speed
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adapter speed 9500
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# Enable faster DCC downloads.
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arm7_9 dcc_downloads enable
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arm7_9 fast_memory_access enable
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# To be able to use external SDRAM, several peripheral configuration registers must
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# be modified. The first change is made to PIO_ASR to select peripheral functions
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# for D15 through D31. The second change is made to the PIO_PDR register to disable
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# this for D15 through D31.
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mww 0xfffff870 0xffff0000
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mww 0xfffff804 0xffff0000
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# The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
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# using CS1. Additionally we want CS3 assigned to NandFlash. Also VDDIO is connected physically on
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# the board to the 1.8V VDC power supply so set the appropriate register bit to notify the micrcontroller.
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mww 0xffffef1c 0x000000a
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# The USB-A9G20 Embedded computer has built-in NandFlash. The exact physical timing characteristics
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# for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
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# four registers in order: SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
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mww 0xffffec30 0x00020002
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mww 0xffffec34 0x04040404
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mww 0xffffec38 0x00070007
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mww 0xffffec3c 0x00030003
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# Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations
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# are based on 2 x Micron LPSDRAM MT48H16M16LFBF-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference
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# for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
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# into the SDRAM_CR register. Using the memory datasheet for the -75 grade part and assuming a master clock
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# of 133.000 MHz then the SDCLK period is equal to 7.6 ns. This means the device requires:
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#
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# CAS latency = 3 cycles
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# TXSR = 10 cycles
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# TRAS = 6 cycles
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# TRCD = 3 cycles
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# TRP = 3 cycles
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# TRC = 9 cycles
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# TWR = 2 cycles
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# 9 column, 13 row, 4 banks
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# refresh equal to or less then 7.8 us for commercial/industrial rated devices
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#
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# Thus SDRAM_CR = 0xa6339279
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mww 0xffffea08 0xa6339279
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# Memory Device Type: SDRAM (low-power would be 0x1)
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mww 0xffffea24 0x00000000
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# Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
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# the starting memory location for the SDRAM.
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mww 0xffffea00 0x00000001
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mww 0x20000000 0
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# Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
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# value into the starting memory location for the SDRAM.
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mww 0xffffea00 0x00000002
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mww 0x20000000 0
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# Now issue an 'Auto-Refresh' command through the SDRAMC_MR register. Follow this operation by writing
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# zero values eight times into the starting memory location for the SDRAM.
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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# Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
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# the starting memory location for the SDRAM.
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mww 0xffffea00 0x3
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mww 0x20000000 0
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# Signal normal mode using the SDRAMC_MR register and follow with a zero value write the starting
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# memory location for the SDRAM.
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mww 0xffffea00 0x0
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mww 0x20000000 0
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# Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
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mww 0xffffea04 0x0000039c
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}
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$_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}
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$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}
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