54 lines
1.5 KiB
INI
54 lines
1.5 KiB
INI
#use combined on interfaces or targets that can't set TRST/SRST separately
|
|
reset_config srst_only srst_pulls_trst
|
|
|
|
if { [info exists CHIPNAME] } {
|
|
set _CHIPNAME $CHIPNAME
|
|
} else {
|
|
set _CHIPNAME at91sam7s
|
|
}
|
|
|
|
if { [info exists ENDIAN] } {
|
|
set _ENDIAN $ENDIAN
|
|
} else {
|
|
set _ENDIAN little
|
|
}
|
|
|
|
if { [info exists CPUTAPID] } {
|
|
set _CPUTAPID $CPUTAPID
|
|
} else {
|
|
set _CPUTAPID 0x3f0f0f0f
|
|
}
|
|
|
|
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
|
|
|
set _TARGETNAME $_CHIPNAME.cpu
|
|
|
|
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
|
|
$_TARGETNAME configure -event reset-init {
|
|
soft_reset_halt
|
|
# RSTC_CR : Reset peripherals
|
|
mww 0xfffffd00 0xa5000004
|
|
# disable watchdog
|
|
mww 0xfffffd44 0x00008000
|
|
# enable user reset
|
|
mww 0xfffffd08 0xa5000001
|
|
# CKGR_MOR : enable the main oscillator
|
|
mww 0xfffffc20 0x00000601
|
|
sleep 10
|
|
# CKGR_PLLR: 96.1097 MHz
|
|
mww 0xfffffc2c 0x00481c0e
|
|
sleep 10
|
|
# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
|
|
mww 0xfffffc30 0x00000007
|
|
sleep 10
|
|
# MC_FMR: flash mode (FWS=1,FMCN=73)
|
|
mww 0xffffff60 0x00490100
|
|
sleep 100
|
|
}
|
|
|
|
$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
|
|
|
|
#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
|
|
set _FLASHNAME $_CHIPNAME.flash
|
|
flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
|