58 lines
1.9 KiB
INI
58 lines
1.9 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# script for stm32u5x family
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# stm32u5x devices support both JTAG and SWD transports.
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32u5x
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}
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source [find target/stm32x5x_common.cfg]
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proc stm32u5x_clock_config {} {
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set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
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# MCU clock is at MSI 4MHz after reset, set MCU freq at 160 MHz with PLL
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# Enable voltage range 1 for frequency above 100 Mhz
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# RCC_AHB3ENR = PWREN
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mww [expr {0x46020C94 + $offset}] 0x00000004
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# delay for register clock enable (read back reg)
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mrw [expr {0x46020C94 + $offset}]
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# PWR_VOSR : VOS Range 1
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mmw [expr {0x4602080C + $offset}] 0x00030000 0
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# while !(PWR_VOSR & VOSRDY)
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while {!([mrw [expr {0x4602080C + $offset}]] & 0x00008000)} {}
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# FLASH_ACR : 4 WS for 160 MHz HCLK
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mww [expr {0x40022000 + $offset}] 0x00000004
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# RCC_PLL1CFGR => PLL1MBOOST=0, PLL1M=0=/1, PLL1FRACEN=0, PLL1SRC=MSI 4MHz
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# PLL1REN=1, PLL1RGE => VCOInputRange=PLLInputRange_4_8
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mww [expr {0x46020C28 + $offset}] 0x00040009
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# Enable EPOD Booster
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mmw [expr {0x4602080C + $offset}] 0x00040000 0
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# while !(PWR_VOSR & BOOSTRDY)
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while {!([mrw [expr {0x4602080C + $offset}]] & 0x00004000)} {}
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# RCC_PLL1DIVR => PLL1P=PLL1Q=PLL1R=000001=/2, PLL1N=0x4F=80
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# fVCO = 4 x 80 /1 = 320
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# SYSCLOCK = fVCO/PLL1R = 320/2 = 160 MHz
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mww [expr {0x46020C34 + $offset}] 0x0101024F
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# RCC_CR |= PLL1ON
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mmw [expr {0x46020C00 + $offset}] 0x01000000 0
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# while !(RCC_CR & PLL1RDY)
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while {!([mrw [expr {0x46020C00 + $offset}]] & 0x02000000)} {}
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# RCC_CFGR1 |= SW_PLL
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mmw [expr {0x46020C1C + $offset}] 0x00000003 0
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# while ((RCC_CFGR1 & SWS) != PLL)
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while {([mrw [expr {0x46020C1C + $offset}]] & 0x0C) != 0x0C} {}
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}
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$_TARGETNAME configure -event reset-init {
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stm32u5x_clock_config
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# Boost JTAG frequency
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adapter speed 4000
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}
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