58 lines
1.5 KiB
INI
58 lines
1.5 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Texas Instruments CC26x0 - ARM Cortex-M3
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#
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# http://www.ti.com
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#
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source [find target/icepick.cfg]
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source [find target/ti-cjtag.cfg]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME cc26x0
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}
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#
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# Main DAP
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#
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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set _DAP_TAPID 0x4BA00477
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
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jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
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#
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# ICEpick-C (JTAG route controller)
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#
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if { [info exists JRC_TAPID] } {
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set _JRC_TAPID $JRC_TAPID
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} else {
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set _JRC_TAPID 0x0B99A02F
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}
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
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jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
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# A start sequence is needed to change from 2-pin cJTAG to 4-pin JTAG
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jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc"
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set _TARGETNAME $_CHIPNAME.cpu
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x4000
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}
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
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cortex_m reset_config vectreset
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