# SPDX-License-Identifier: GPL-2.0-or-later

# Xilinx Spartan3 generation
# https://www.xilinx.com/support/documentation/user_guides/ug331.pdf

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME xc3s
}

# Table 12-4 in https://www.xilinx.com/support/documentation/user_guides/ug332.pdf
# the 4 top bits (28:31) are the die stepping, ignore them.
jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
	-expected-id 0x02210093 \
	-expected-id 0x02218093 \
	-expected-id 0x02220093 \
	-expected-id 0x02228093 \
	-expected-id 0x02230093 \
	-expected-id 0x02610093 \
	-expected-id 0x02618093 \
	-expected-id 0x02620093 \
	-expected-id 0x02628093 \
	-expected-id 0x02630093 \
	-expected-id 0x03840093 \
	-expected-id 0x0384E093 \
	-expected-id 0x01C10093 \
	-expected-id 0x01C1A093 \
	-expected-id 0x01C22093 \
	-expected-id 0x01C2E093 \
	-expected-id 0x01C3A093 \
	-expected-id 0x0140C093 \
	-expected-id 0x01414093 \
	-expected-id 0x0141C093 \
	-expected-id 0x01428093 \
	-expected-id 0x01434093 \
	-expected-id 0x01440093 \
	-expected-id 0x01448093 \
	-expected-id 0x01450093

pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap

source [find fpga/xilinx-dna.cfg]