Zero the input buffer

This reverts commit de71abeaba.

src/rtos/riscv_debug.c

@@ -129,6 +129,18 @@ static int riscv_gdb_thread_packet(struct connection *connection, const char *pa
 			return ERROR_OK;
 		}
 
+		if (strncmp(packet, "qTStatus", 8) == 0) {
+			gdb_put_packet(connection, "T0", strlen("T0"));
+			return ERROR_OK;
+		}
+
+		if (strncmp(packet, "qC", 2) == 0) {
+			char rep_str[32];
+			snprintf(rep_str, 32, "QC%d", rtos->current_threadid);
+			gdb_put_packet(connection, rep_str, strlen(rep_str));
+			return ERROR_OK;
+		}
+
 		return GDB_THREAD_PACKET_NOT_CONSUMED;
 
 	case 'Q':
@@ -248,6 +260,7 @@ static int riscv_gdb_v_packet(struct connection *connection, const char *packet,
 	if (strcmp(packet_stttrr, "vCont;c") == 0) {
 		target_call_event_callbacks(target, TARGET_EVENT_GDB_START);
 		target_call_event_callbacks(target, TARGET_EVENT_RESUME_START);
+		riscv_set_all_rtos_harts(target);
 		riscv_openocd_resume(target, 1, 0, 0, 0);
 		target->state = TARGET_RUNNING;
 		gdb_set_frontend_state_running(connection);

src/server/gdb_server.c

@@ -96,7 +96,7 @@ struct gdb_connection {
 	char *thread_list;
 };
 
-#if 0
+#if 1
 #define _DEBUG_GDB_IO_
 #endif
 
@@ -779,6 +779,10 @@ static void gdb_signal_reply(struct target *target, struct connection *connectio
 		gdb_connection->ctrl_c = 0;
 	}
 
+	char sig_reply_str[46];
+	memset(sig_reply_str, '\0', 46);
+	strncpy(sig_reply_str, sig_reply, 46);
+	LOG_DEBUG("signal reply: %s", sig_reply_str);
 	gdb_put_packet(connection, sig_reply, sig_reply_len);
 	gdb_connection->frontend_state = TARGET_HALTED;
 }

src/target/riscv/batch.c

@@ -51,7 +51,7 @@ int riscv_batch_run(struct riscv_batch *batch)
 
 	keep_alive();
 
-	LOG_DEBUG("running a batch of %ld scans", (long)batch->used_scans);
+	LOG_DEBUG_IO("running a batch of %ld scans", (long)batch->used_scans);
 	riscv_batch_add_nop(batch);
 
 	for (size_t i = 0; i < batch->used_scans; ++i) {
@@ -60,7 +60,7 @@ int riscv_batch_run(struct riscv_batch *batch)
 			jtag_add_runtest(batch->idle_count, TAP_IDLE);
 	}
 
-	LOG_DEBUG("executing queue");
+	LOG_DEBUG_IO("executing queue");
 	if (jtag_execute_queue() != ERROR_OK) {
 		LOG_ERROR("Unable to execute JTAG queue");
 		return ERROR_FAIL;
@@ -102,7 +102,7 @@ size_t riscv_batch_add_dmi_read(struct riscv_batch *batch, unsigned address)
 	riscv_batch_add_nop(batch);
 
 	batch->read_keys[batch->read_keys_used] = batch->used_scans - 1;
-	LOG_DEBUG("read key %u for batch 0x%p is %u (0x%p)",
+	LOG_DEBUG_IO("read key %u for batch 0x%p is %u (0x%p)",
 			(unsigned) batch->read_keys_used, batch, (unsigned) (batch->used_scans - 1),
 			batch->data_in + sizeof(uint64_t) * (batch->used_scans + 1));
 	return batch->read_keys_used++;
@@ -135,7 +135,7 @@ void riscv_batch_add_nop(struct riscv_batch *batch)
 	riscv_fill_dmi_nop_u64(batch->target, (char *)field->in_value);
 	batch->last_scan = RISCV_SCAN_TYPE_NOP;
 	batch->used_scans++;
-	LOG_DEBUG("  added NOP with in_value=0x%p", field->in_value);
+	LOG_DEBUG_IO("  added NOP with in_value=0x%p", field->in_value);
 }
 
 void dump_field(const struct scan_field *field)
@@ -143,7 +143,7 @@ void dump_field(const struct scan_field *field)
 	static const char * const op_string[] = {"-", "r", "w", "?"};
 	static const char * const status_string[] = {"+", "?", "F", "b"};
 
-	if (debug_level < LOG_LVL_DEBUG)
+	if (debug_level < LOG_LVL_DEBUG_IO)
 		return;
 
 	assert(field->out_value != NULL);
@@ -158,14 +158,14 @@ void dump_field(const struct scan_field *field)
 		unsigned int in_data = get_field(in, DTM_DMI_DATA);
 		unsigned int in_address = in >> DTM_DMI_ADDRESS_OFFSET;
 
-		log_printf_lf(LOG_LVL_DEBUG,
+		log_printf_lf(LOG_LVL_DEBUG_IO,
 				__FILE__, __LINE__, __PRETTY_FUNCTION__,
 				"%db %s %08x @%02x -> %s %08x @%02x",
 				field->num_bits,
 				op_string[out_op], out_data, out_address,
 				status_string[in_op], in_data, in_address);
 	} else {
-		log_printf_lf(LOG_LVL_DEBUG,
+		log_printf_lf(LOG_LVL_DEBUG_IO,
 				__FILE__, __LINE__, __PRETTY_FUNCTION__, "%db %s %08x @%02x -> ?",
 				field->num_bits, op_string[out_op], out_data, out_address);
 	}

src/target/riscv/riscv-013.c

@@ -1718,13 +1718,38 @@ static void write_to_buf(uint8_t *buffer, uint64_t value, unsigned size)
 
 static int execute_fence(struct target *target)
 {
-	struct riscv_program program;
-	riscv_program_init(&program, target);
-	riscv_program_fence(&program);
-	int result = riscv_program_exec(&program, target);
-	if (result != ERROR_OK)
-		LOG_ERROR("Unable to execute fence");
-	return result;
+	int old_hartid = riscv_current_hartid(target);
+
+	/* FIXME: For non-coherent systems we need to flush the caches right
+	 * here, but there's no ISA-defined way of doing that. */
+	{
+		struct riscv_program program;
+		riscv_program_init(&program, target);
+		riscv_program_fence_i(&program);
+		riscv_program_fence(&program);
+		int result = riscv_program_exec(&program, target);
+		if (result != ERROR_OK)
+			LOG_DEBUG("Unable to execute pre-fence");
+	}
+
+	for (int i = 0; i < riscv_count_harts(target); ++i) {
+		if (!riscv_hart_enabled(target, i))
+			continue;
+
+		riscv_set_current_hartid(target, i);
+
+		struct riscv_program program;
+		riscv_program_init(&program, target);
+		riscv_program_fence_i(&program);
+		riscv_program_fence(&program);
+		int result = riscv_program_exec(&program, target);
+		if (result != ERROR_OK)
+			LOG_DEBUG("Unable to execute fence on hart %d", i);
+	}
+
+	riscv_set_current_hartid(target, old_hartid);
+
+	return ERROR_OK;
 }
 
 static void log_memory_access(target_addr_t address, uint64_t value,
@@ -1999,6 +2024,8 @@ static int read_memory_progbuf(struct target *target, target_addr_t address,
 
 	select_dmi(target);
 
+	memset(buffer, 0, count*size);
+
 	/* s0 holds the next address to write to
 	 * s1 holds the next data value to write
 	 */
@@ -2034,28 +2061,38 @@ static int read_memory_progbuf(struct target *target, target_addr_t address,
 		return ERROR_FAIL;
 	riscv_program_write(&program);
 
-	/* Write address to S0, and execute buffer. */
+	/* read_addr is the next address that the hart will read from, which is the
+	 * value in s0. */
+	riscv_addr_t read_addr = address;
+	/* The next address that we need to receive data for. */
+	riscv_addr_t receive_addr = address;
+	riscv_addr_t fin_addr = address + (count * size);
+
+	/* Write address to S0, and execute buffer until we end up successfully
+	 * reading an actual word from memory.  This is necessary because
+	 * Eclipse might ask us to read memory before the start of a block. */
 	result = register_write_direct(target, GDB_REGNO_S0, address);
-	if (result != ERROR_OK)
-		goto error;
 	uint32_t command = access_register_command(GDB_REGNO_S1, riscv_xlen(target),
 				AC_ACCESS_REGISTER_TRANSFER |
 				AC_ACCESS_REGISTER_POSTEXEC);
-	result = execute_abstract_command(target, command);
-	if (result != ERROR_OK)
-		goto error;
 
-	/* First read has just triggered. Result is in s1. */
+	do {
+		LOG_DEBUG("Performing first read at 0x%" PRIx64, read_addr);
+		result = register_write_direct(target, GDB_REGNO_S0, read_addr);
+		if (result != ERROR_OK)
+			goto error;
+		result = execute_abstract_command(target, command);
+		riscv013_clear_abstract_error(target);
+		read_addr += size;
+		if (result != ERROR_OK)
+			receive_addr += size;
+	} while (result != ERROR_OK && read_addr < fin_addr);
+
+	/* First valid read has just triggered. Result is in s1. */
 
 	dmi_write(target, DMI_ABSTRACTAUTO,
 			1 << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET);
 
-	/* read_addr is the next address that the hart will read from, which is the
-	 * value in s0. */
-	riscv_addr_t read_addr = address + size;
-	/* The next address that we need to receive data for. */
-	riscv_addr_t receive_addr = address;
-	riscv_addr_t fin_addr = address + (count * size);
 	unsigned skip = 1;
 	while (read_addr < fin_addr) {
 		LOG_DEBUG("read_addr=0x%" PRIx64 ", receive_addr=0x%" PRIx64
@@ -2161,11 +2198,22 @@ static int read_memory_progbuf(struct target *target, target_addr_t address,
 						1 << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET);
 				break;
 			default:
-				LOG_ERROR("error when reading memory, abstractcs=0x%08lx", (long)abstractcs);
+				LOG_DEBUG("error when reading memory, abstractcs=0x%08lx", (long)abstractcs);
 				riscv013_clear_abstract_error(target);
 				riscv_batch_free(batch);
 				result = ERROR_FAIL;
-				goto error;
+				/* Eclipse attempts to pre-buffer some data
+				 * before an address, so here we retry on
+				 * failing reads by just moving on to the next
+				 * address. */
+				dmi_write(target, DMI_ABSTRACTAUTO, 0);
+				next_read_addr = read_addr + size;
+				if (register_write_direct(target, GDB_REGNO_S0, next_read_addr) != ERROR_OK)
+					goto error;
+				dmi_write(target, DMI_COMMAND, command);
+				dmi_write(target, DMI_ABSTRACTAUTO,
+						1 << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET);
+				break;
 		}
 
 		/* Now read whatever we got out of the batch. */
@@ -2899,19 +2947,7 @@ int riscv013_dmi_write_u64_bits(struct target *target)
 
 static int maybe_execute_fence_i(struct target *target)
 {
-	RISCV013_INFO(info);
-	RISCV_INFO(r);
-	if (info->progbufsize + r->impebreak >= 2) {
-		struct riscv_program program;
-		riscv_program_init(&program, target);
-		if (riscv_program_fence_i(&program) != ERROR_OK)
-			return ERROR_FAIL;
-		if (riscv_program_exec(&program, target) != ERROR_OK) {
-			LOG_ERROR("Failed to execute fence.i");
-			return ERROR_FAIL;
-		}
-	}
-	return ERROR_OK;
+	return execute_fence(target);
 }
 
 /* Helper Functions. */

src/target/riscv/riscv.c

@@ -18,6 +18,8 @@
 #include "gdb_regs.h"
 #include "rtos/rtos.h"
 
+#define RISCV_DEBUG_POLL
+
 /**
  * Since almost everything can be accomplish by scanning the dbus register, all
  * functions here assume dbus is already selected. The exception are functions
@@ -263,6 +265,8 @@ static int riscv_init_target(struct command_context *cmd_ctx,
 	select_dbus.num_bits = target->tap->ir_length;
 	select_idcode.num_bits = target->tap->ir_length;
 
+	target->debug_reason = DBG_REASON_DBGRQ;
+
 	return ERROR_OK;
 }
 
@@ -495,6 +499,8 @@ static int add_trigger(struct target *target, struct trigger *trigger)
 int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
 	if (breakpoint->type == BKPT_SOFT) {
+		LOG_DEBUG("Adding software breakpoint at 0x%016lx", breakpoint->address);
+
 		if (target_read_memory(target, breakpoint->address, breakpoint->length, 1,
 					breakpoint->orig_instr) != ERROR_OK) {
 			LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR,
@@ -757,9 +763,12 @@ static int old_or_new_riscv_resume(
 static int riscv_select_current_hart(struct target *target)
 {
 	RISCV_INFO(r);
-	if (r->rtos_hartid != -1 && riscv_rtos_enabled(target))
+	if (riscv_rtos_enabled(target)) {
+		if (r->rtos_hartid == -1)
+			r->rtos_hartid = target->rtos->current_threadid - 1;
+
 		return riscv_set_current_hartid(target, r->rtos_hartid);
-	else
+	} else
 		return riscv_set_current_hartid(target, target->coreid);
 }
 
@@ -1001,8 +1010,15 @@ static enum riscv_poll_hart riscv_poll_hart(struct target *target, int hartid)
 /*** OpenOCD Interface ***/
 int riscv_openocd_poll(struct target *target)
 {
+#ifdef RISCV_DEBUG_POLL
 	LOG_DEBUG("polling all harts");
+#endif
 	int halted_hart = -1;
+        int old_debug_level = debug_level;
+#ifdef RISCV_DEBUG_POLL
+#else
+        debug_level = LOG_LVL_INFO;
+#endif
 	if (riscv_rtos_enabled(target)) {
 		/* Check every hart for an event. */
 		for (int i = 0; i < riscv_count_harts(target); ++i) {
@@ -1015,14 +1031,24 @@ int riscv_openocd_poll(struct target *target)
 				halted_hart = i;
 				break;
 			case RPH_ERROR:
+				debug_level = old_debug_level;
 				return ERROR_FAIL;
 			}
 		}
 		if (halted_hart == -1) {
+#ifdef RISCV_DEBUG_POLL
 			LOG_DEBUG("  no harts just halted, target->state=%d", target->state);
+#endif
+			debug_level = old_debug_level;
 			return ERROR_OK;
 		}
+#ifdef RISCV_DEBUG_POLL
 		LOG_DEBUG("  hart %d halted", halted_hart);
+#else
+		debug_level = old_debug_level;
+		LOG_DEBUG("hart %d halted", halted_hart);
+		debug_level = LOG_LVL_INFO;
+#endif
 
 		/* If we're here then at least one hart triggered.  That means
 		 * we want to go and halt _every_ hart in the system, as that's
@@ -1035,13 +1061,23 @@ int riscv_openocd_poll(struct target *target)
 	} else {
 		enum riscv_poll_hart out = riscv_poll_hart(target,
 				riscv_current_hartid(target));
-		if (out == RPH_NO_CHANGE || out == RPH_DISCOVERED_RUNNING)
+		if (out == RPH_NO_CHANGE || out == RPH_DISCOVERED_RUNNING) {
+			debug_level = old_debug_level;
 			return ERROR_OK;
-		else if (out == RPH_ERROR)
+		}
+		else if (out == RPH_ERROR) {
+			debug_level = old_debug_level;
 			return ERROR_FAIL;
+		}
 
 		halted_hart = riscv_current_hartid(target);
+#ifdef RISCV_DEBUG_POLL
 		LOG_DEBUG("  hart %d halted", halted_hart);
+#else
+		debug_level = old_debug_level;
+		LOG_DEBUG("hart %d halted", halted_hart);
+		debug_level = LOG_LVL_INFO;
+#endif
 	}
 
 	target->state = TARGET_HALTED;
@@ -1062,16 +1098,19 @@ int riscv_openocd_poll(struct target *target)
 		target->debug_reason = DBG_REASON_UNDEFINED;
 		break;
 	case RISCV_HALT_ERROR:
+		debug_level = old_debug_level;
 		return ERROR_FAIL;
 	}
 
 	if (riscv_rtos_enabled(target)) {
+		LOG_DEBUG("    setting RTOS threaded to %d+1", halted_hart);
 		target->rtos->current_threadid = halted_hart + 1;
 		target->rtos->current_thread = halted_hart + 1;
 	}
 
 	target->state = TARGET_HALTED;
 	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+	debug_level = old_debug_level;
 	return ERROR_OK;
 }
 
@@ -1089,8 +1128,12 @@ int riscv_openocd_halt(struct target *target)
 
 	register_cache_invalidate(target->reg_cache);
 	if (riscv_rtos_enabled(target)) {
-		target->rtos->current_threadid = r->rtos_hartid + 1;
-		target->rtos->current_thread = r->rtos_hartid + 1;
+		if (r->rtos_hartid != -1) {
+			LOG_DEBUG("halt requested on RTOS hartid %d", r->rtos_hartid);
+			target->rtos->current_threadid = r->rtos_hartid + 1;
+			target->rtos->current_thread = r->rtos_hartid + 1;
+		} else
+			LOG_DEBUG("halt requested, but no known RTOS hartid");
 	}
 
 	target->state = TARGET_HALTED;
@@ -1591,6 +1634,8 @@ int riscv_halt_all_harts(struct target *target)
 		riscv_halt_one_hart(target, i);
 	}
 
+	riscv_invalidate_register_cache(target);
+
 	return ERROR_OK;
 }
 
@@ -1643,7 +1688,7 @@ int riscv_step_rtos_hart(struct target *target)
 	if (riscv_rtos_enabled(target)) {
 		hartid = r->rtos_hartid;
 		if (hartid == -1) {
-			LOG_USER("GDB has asked me to step \"any\" thread, so I'm stepping hart 0.");
+			LOG_DEBUG("GDB has asked me to step \"any\" thread, so I'm stepping hart 0.");
 			hartid = 0;
 		}
 	}
@@ -1716,14 +1761,15 @@ int riscv_set_current_hartid(struct target *target, int hartid)
 	if (!target_was_examined(target))
 		return ERROR_OK;
 
+#if 0
 	/* Avoid invalidating the register cache all the time. */
 	if (r->registers_initialized
 			&& (!riscv_rtos_enabled(target) || (previous_hartid == hartid))
-			&& target->reg_cache->reg_list[GDB_REGNO_ZERO].size == (unsigned)riscv_xlen(target)
-			&& (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) {
+			&& target->reg_cache->reg_list[GDB_REGNO_ZERO].size == (unsigned)riscv_xlen(target)) {
 		return ERROR_OK;
 	} else
 		LOG_DEBUG("Initializing registers: xlen=%d", riscv_xlen(target));
+#endif
 
 	riscv_invalidate_register_cache(target);
 	return ERROR_OK;
@@ -1805,7 +1851,15 @@ int riscv_get_register_on_hart(struct target *target, riscv_reg_t *value,
 		int hartid, enum gdb_regno regid)
 {
 	RISCV_INFO(r);
+
+        if (hartid != riscv_current_hartid(target))
+		riscv_invalidate_register_cache(target);
+
 	int result = r->get_register(target, value, hartid, regid);
+
+        if (hartid != riscv_current_hartid(target))
+		riscv_invalidate_register_cache(target);
+
 	LOG_DEBUG("[%d] %s: %" PRIx64, hartid, gdb_regno_name(regid), *value);
 	return result;
 }

src/target/startup.tcl

@@ -203,7 +203,6 @@ proc init_target_events {} {
 	foreach t $targets {
 		set_default_target_event $t gdb-flash-erase-start "reset init"
 		set_default_target_event $t gdb-flash-write-end "reset halt"
-		set_default_target_event $t gdb-attach "halt"
 	}
 }