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2 Commits
riscv ... race

Author SHA1 Message Date
Palmer Dabbelt 8aeebdcef7 Work around another race condition 2017-05-09 18:54:14 -07:00
Palmer Dabbelt 50c11cd7d0 Work around a race condition in an old debug spec 2017-05-09 18:03:33 -07:00
1 changed files with 3 additions and 2 deletions
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5
src/target/riscv/riscv-013.c
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@ -341,6 +341,7 @@ static dmi_status_t dmi_scan(struct target *target, uint16_t *address_in,
int idle_count = info->dmi_busy_delay;
if (exec)
idle_count += info->ac_busy_delay;
idle_count += 10;
if (idle_count) {
jtag_add_runtest(idle_count, TAP_IDLE);
@ -1329,7 +1330,7 @@ static int read_memory(struct target *target, uint32_t address,
struct riscv_batch *batch = riscv_batch_alloc(
target,
1024,
info->dmi_busy_delay + info->ac_busy_delay);
info->dmi_busy_delay + info->ac_busy_delay + 10);
size_t reads = 0;
size_t rereads = reads;
@ -1522,7 +1523,7 @@ static int write_memory(struct target *target, uint32_t address,
struct riscv_batch *batch = riscv_batch_alloc(
target,
1024,
info->dmi_busy_delay + info->ac_busy_delay);
info->dmi_busy_delay + info->ac_busy_delay + 10);
for (riscv_addr_t i = start; i < count; ++i) {
riscv_addr_t offset = size*i;