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2 Commits
Author | SHA1 | Date |
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8aeebdcef7 | |
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50c11cd7d0 |
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@ -341,6 +341,7 @@ static dmi_status_t dmi_scan(struct target *target, uint16_t *address_in,
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int idle_count = info->dmi_busy_delay;
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int idle_count = info->dmi_busy_delay;
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if (exec)
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if (exec)
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idle_count += info->ac_busy_delay;
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idle_count += info->ac_busy_delay;
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idle_count += 10;
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if (idle_count) {
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if (idle_count) {
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jtag_add_runtest(idle_count, TAP_IDLE);
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jtag_add_runtest(idle_count, TAP_IDLE);
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@ -1329,7 +1330,7 @@ static int read_memory(struct target *target, uint32_t address,
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struct riscv_batch *batch = riscv_batch_alloc(
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struct riscv_batch *batch = riscv_batch_alloc(
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target,
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target,
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1024,
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1024,
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info->dmi_busy_delay + info->ac_busy_delay);
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info->dmi_busy_delay + info->ac_busy_delay + 10);
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size_t reads = 0;
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size_t reads = 0;
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size_t rereads = reads;
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size_t rereads = reads;
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@ -1522,7 +1523,7 @@ static int write_memory(struct target *target, uint32_t address,
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struct riscv_batch *batch = riscv_batch_alloc(
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struct riscv_batch *batch = riscv_batch_alloc(
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target,
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target,
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1024,
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1024,
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info->dmi_busy_delay + info->ac_busy_delay);
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info->dmi_busy_delay + info->ac_busy_delay + 10);
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for (riscv_addr_t i = start; i < count; ++i) {
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for (riscv_addr_t i = start; i < count; ++i) {
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riscv_addr_t offset = size*i;
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riscv_addr_t offset = size*i;
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