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@ -1213,6 +1213,95 @@ int riscv_resume_prep_all_harts(struct target *target)
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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/* state must be riscv_reg_t state[RISCV_MAX_HWBPS] = {0}; */
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static int disable_triggers(struct target *target, riscv_reg_t *state)
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{
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RISCV_INFO(r);
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LOG_DEBUG("deal with triggers");
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if (riscv_enumerate_triggers(target) != ERROR_OK)
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return ERROR_FAIL;
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int hartid = riscv_current_hartid(target);
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if (r->manual_hwbp_set) {
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/* Look at every trigger that may have been set. */
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riscv_reg_t tselect;
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if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
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return ERROR_FAIL;
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for (unsigned t = 0; t < r->trigger_count[hartid]; t++) {
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if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
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return ERROR_FAIL;
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riscv_reg_t tdata1;
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if (riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1) != ERROR_OK)
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return ERROR_FAIL;
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if (tdata1 & MCONTROL_DMODE(riscv_xlen(target))) {
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state[t] = tdata1;
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if (riscv_set_register(target, GDB_REGNO_TDATA1, 0) != ERROR_OK)
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return ERROR_FAIL;
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}
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}
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if (riscv_set_register(target, GDB_REGNO_TSELECT, tselect) != ERROR_OK)
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return ERROR_FAIL;
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} else {
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/* Just go through the triggers we manage. */
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struct watchpoint *watchpoint = target->watchpoints;
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int i = 0;
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while (watchpoint) {
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LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->set);
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state[i] = watchpoint->set;
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if (watchpoint->set) {
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if (riscv_remove_watchpoint(target, watchpoint) != ERROR_OK)
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return ERROR_FAIL;
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}
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watchpoint = watchpoint->next;
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i++;
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}
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}
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return ERROR_OK;
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}
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static int enable_triggers(struct target *target, riscv_reg_t *state)
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{
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RISCV_INFO(r);
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int hartid = riscv_current_hartid(target);
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if (r->manual_hwbp_set) {
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/* Look at every trigger that may have been set. */
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riscv_reg_t tselect;
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if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
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return ERROR_FAIL;
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for (unsigned t = 0; t < r->trigger_count[hartid]; t++) {
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if (state[t] != 0) {
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if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
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return ERROR_FAIL;
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if (riscv_set_register(target, GDB_REGNO_TDATA1, state[t]) != ERROR_OK)
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return ERROR_FAIL;
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}
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}
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if (riscv_set_register(target, GDB_REGNO_TSELECT, tselect) != ERROR_OK)
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return ERROR_FAIL;
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} else {
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struct watchpoint *watchpoint = target->watchpoints;
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int i = 0;
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while (watchpoint) {
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LOG_DEBUG("watchpoint %d: cleared=%" PRId64, i, state[i]);
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if (state[i]) {
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if (riscv_add_watchpoint(target, watchpoint) != ERROR_OK)
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return ERROR_FAIL;
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}
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watchpoint = watchpoint->next;
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i++;
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}
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}
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return ERROR_OK;
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}
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/**
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/**
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* Get everything ready to resume.
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* Get everything ready to resume.
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*/
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*/
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@ -1228,39 +1317,16 @@ static int resume_prep(struct target *target, int current,
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if (target->debug_reason == DBG_REASON_WATCHPOINT) {
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if (target->debug_reason == DBG_REASON_WATCHPOINT) {
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/* To be able to run off a trigger, disable all the triggers, step, and
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/* To be able to run off a trigger, disable all the triggers, step, and
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* then resume as usual. */
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* then resume as usual. */
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struct watchpoint *watchpoint = target->watchpoints;
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riscv_reg_t trigger_state[RISCV_MAX_HWBPS] = {0};
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bool trigger_temporarily_cleared[RISCV_MAX_HWBPS] = {0};
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int i = 0;
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if (disable_triggers(target, trigger_state) != ERROR_OK)
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int result = ERROR_OK;
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return ERROR_FAIL;
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while (watchpoint && result == ERROR_OK) {
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LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->set);
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trigger_temporarily_cleared[i] = watchpoint->set;
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if (watchpoint->set)
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result = riscv_remove_watchpoint(target, watchpoint);
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watchpoint = watchpoint->next;
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i++;
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}
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if (result == ERROR_OK)
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if (old_or_new_riscv_step(target, true, 0, false) != ERROR_OK)
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result = old_or_new_riscv_step(target, true, 0, false);
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return ERROR_FAIL;
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watchpoint = target->watchpoints;
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if (enable_triggers(target, trigger_state) != ERROR_OK)
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i = 0;
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return ERROR_FAIL;
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while (watchpoint) {
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LOG_DEBUG("watchpoint %d: cleared=%d", i, trigger_temporarily_cleared[i]);
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if (trigger_temporarily_cleared[i]) {
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if (result == ERROR_OK)
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result = riscv_add_watchpoint(target, watchpoint);
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else
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riscv_add_watchpoint(target, watchpoint);
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}
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watchpoint = watchpoint->next;
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i++;
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}
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if (result != ERROR_OK)
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return result;
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}
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}
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if (r->is_halted) {
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if (r->is_halted) {
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@ -2133,6 +2199,10 @@ int riscv_openocd_step(
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if (!current)
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if (!current)
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riscv_set_register(target, GDB_REGNO_PC, address);
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riscv_set_register(target, GDB_REGNO_PC, address);
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riscv_reg_t trigger_state[RISCV_MAX_HWBPS] = {0};
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if (disable_triggers(target, trigger_state) != ERROR_OK)
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return ERROR_FAIL;
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int out = riscv_step_rtos_hart(target);
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int out = riscv_step_rtos_hart(target);
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if (out != ERROR_OK) {
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if (out != ERROR_OK) {
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LOG_ERROR("unable to step rtos hart");
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LOG_ERROR("unable to step rtos hart");
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@ -2140,6 +2210,10 @@ int riscv_openocd_step(
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}
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}
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register_cache_invalidate(target->reg_cache);
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register_cache_invalidate(target->reg_cache);
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if (enable_triggers(target, trigger_state) != ERROR_OK)
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return ERROR_FAIL;
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target->state = TARGET_RUNNING;
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target->state = TARGET_RUNNING;
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target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
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target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
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target->state = TARGET_HALTED;
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target->state = TARGET_HALTED;
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@ -3563,6 +3637,17 @@ static int register_set(struct reg *reg, uint8_t *buf)
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memcpy(reg->value, buf, DIV_ROUND_UP(reg->size, 8));
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memcpy(reg->value, buf, DIV_ROUND_UP(reg->size, 8));
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reg->valid = gdb_regno_cacheable(reg->number, true);
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reg->valid = gdb_regno_cacheable(reg->number, true);
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if (reg->number == GDB_REGNO_TDATA1 ||
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reg->number == GDB_REGNO_TDATA2) {
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r->manual_hwbp_set = true;
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/* When enumerating triggers, we clear any triggers with DMODE set,
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* assuming they were left over from a previous debug session. So make
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* sure that is done before a user might be setting their own triggers.
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*/
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if (riscv_enumerate_triggers(target) != ERROR_OK)
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return ERROR_FAIL;
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}
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if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
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if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
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if (!r->set_register_buf) {
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if (!r->set_register_buf) {
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LOG_ERROR("Writing register %s not supported on this RISC-V target.",
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LOG_ERROR("Writing register %s not supported on this RISC-V target.",
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