Commit Graph

9063 Commits

Author SHA1 Message Date
Tarek BOCHKATI d6541a811d doc: add missing target types
missing target types are arm946e, avr32_ap7k, cortex_r4, dsp5680xx,
hla_target, mips_mips64, nds32_v2, nds32_v3, nds32_v3m, quark_d20xx,
quark_x10xx, riscv, stm8 and testee

Change-Id: I38f6ed78ee88c09add4b779cd409ebb1e219304f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5487
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@casualhacker.net>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-27 07:14:38 +00:00
Tarek BOCHKATI 8f221f32bc doc: enhance target types description
target types are sorted alphabetically
minor changes for some precision:
 - cortex_a : it's an ARMv7-A core
 - cortex_m : besides the ARMv7-M it support the v6-M and v8-M cores

Change-Id: I37ade2392fe3948fba4156a2831bbd8739fa9993
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5486
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-27 07:12:53 +00:00
Tarek BOCHKATI af69f5ad0b doc: fix OpenRISC target documentation
OpenRISC correct target name is 'or1k' not 'openrisc'
http://openocd.zylin.com/3096 introduced a conflict between 'openrisc'
and 'ls1_sap' documentations

Change-Id: Iedebbf9809300e1272334c5b63d0b31a41062282
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5485
Tested-by: jenkins
Reviewed-by: Esben Haabendal <esbenhaabendal@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-27 07:11:45 +00:00
Evgeniy Didin f00070edaf target/arc_cmd: Improve argument checks for commands
Add more argument check for "add-reg" command.

Changes since first revision:
-Removed arguments limitation(50 maximum) for "arc_set_reg_exists".

Changes:
25.03:
Removed inconsistency in "add-reg" function. Actually
"-type" option is optional and if it is not set,
register type is "int".

Change-Id: Ia21e6baf4fbda162f7811cd0fe305fc86ddafcfd
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5523
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-27 07:09:41 +00:00
Marc Schink 5ceae0eef4 target: Add possibility to remove all breakpoints
Change-Id: I46acd57956846d66bef974e0538452462b197cd0
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4916
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-26 19:30:45 +00:00
Marc Schink 9960e805b3 target: Add function to remove all breakpoints
Change-Id: I4718926844a2c8bcfd78d7a8792f6ded293548ef
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4915
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-26 19:30:34 +00:00
Lars Poeschel d9ffe75e25 avrf.c: Add ATmega256RFR2 to known flash list
This adds the ATmega256RFR2 to the list of know devices for flashing.

Change-Id: Ib24a508762aaa84ba08ba37409db2ae674b46288
Signed-off-by: Lars Pöschel <poeschell+openocd@mailbox.org>
Reviewed-on: http://openocd.zylin.com/5504
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-24 21:34:35 +00:00
Lars Poeschel a708b6d25e avrf.c: Use extended addressing for flash > 0x20000
The current method used for flash addressing uses 16 bit. Every access
to flash is 16 bit wide. With 16 address bits one can address 0x10000
unique locations á 16 bits thats 0x20000 bytes.
For flashes bigger than that avrs have an extended addressing with more
than 16 address bits. This is now implemented and used for flashs larger
than 0x20000 bytes.

Change-Id: Id8b6337dde3830fb3c56b9042872e040bb67c12d
Signed-off-by: Lars Pöschel <poeschell+openocd@mailbox.org>
Reviewed-on: http://openocd.zylin.com/5502
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-24 21:34:18 +00:00
Antonio Borneo 85dc630113 jtag: fix command "adapter [de]assert" with dap direct
The commit fafe6dfc9c ("adapter: add command "adapter [de]assert
srst|trst [[de]assert srst|trst]"") was proposed in gerrit well
before commit a61ec3c1d7 ("adi_v5_dapdirect: add support for
adapter drivers that provide DAP API") get merged, so it didn't
include a complete support for dap direct.
The merge upstream of the two commits lacks the support by command
"adapter [de]assert" for dap direct

Let command command "adapter [de]assert" handle dap direct.

Change-Id: I1a69f8ee877c8fd57598ed4ad9d71da61d15457c
Fixes: commit fafe6dfc9c ("adapter: add command "adapter [de]assert srst|trst [[de]assert srst|trst]"")
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5515
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-24 17:27:39 +00:00
Antonio Borneo b7c13323e7 doc: fix texinfo files attributes on Windows
While installing git on Windows, the user is prompted by a dialog
"Configuring the line ending conversions" to select the value for
the git property "core.autocrlf". The default choice proposed by
the installer is "Checkout Windows-style, commit Unix-style line
endings", that corresponds to "core.autocrlf=true".
Even if the dialog provides technical explanation of the different
choices, most users will blindly accept the default proposal.

With "core.autocrlf=true" git will convert to DOS mode all the
text files during "clone" (so can be edited by any crap Windows
tool) and convert back to UNIX mode during "push" operation.
While this is safe enough for C and TCL files, it breaks the
texinfo files.
The trailing '@' character used for command continuation in
	https://www.gnu.org/software/texinfo/manual/texinfo/html_node/Def-Cmd-Continuation-Lines.html
does not accept being followed by CR+LF (DOS mode), generating a
build error. Same error can be replicated on Linux by passing the
file doc/openocd.texi through "unix2dos" command.
Tentative to fix this has already been proposed in
	http://openocd.zylin.com/5294
	http://openocd.zylin.com/5413
by breaking the command continuation syntax, which is a no go.
The correct fix would require to force/suggest all the Windows
users to get rid of the crap DOS mode, but this could have side
effects.

To workaround the issue, add a .gitattributes file in the doc
folder, specifying a local conversion attribute for the files .txt
and .texi in the doc folder and overriding the eventual incorrect
global value of "core.autocrlf" selected during installation.
The local attribute "text eol=lf" is equivalent to the global one
"core.autocrlf=input".

Change-Id: I468a8f8125b6bc4628fce6c66eb082824ba3413f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5499
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-24 17:20:19 +00:00
Edward Fewell 4d7c48fb80 tcl/target: Enable using vectreset for CC3320SF targets
On CC32xx family of devices, sysrequest is disabled, and
vectreset is blocked by the boot loader (stops in a while(1)
statement). srst reset can leave the target in a state
that prevents debug.

This change enables using vectreset on SF variants by
moving the PC to the start of the user application in
internal flash. This allows for a more reliable reset,
but with two caveats:

1) This only works for the SF variant with internal
   flash.

2) This only resets the CPU and not any peripherals.

Tested on CC3220SF rev B Launchpad in both SWD and
JTAG modes. Confirmed proper behavior of reset,
reset init, reset halt, and reset run commands.

Update: reworked per comment in code review. Re-tested
with CC3220SF Launchpad as both CC3220SF and as
CC32xx board to confirm reset behavior as expected.

Update: Added adapter srst delay 1100 line to the
CC3200 LaunchXL configuration file.

Change-Id: Ibc042d785c846c2223ae55b8f2410b75ed2df354
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5489
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-24 17:18:31 +00:00
Edward Fewell d35c44c743 drivers: xds110: Add support of alternate XDS110 configurations
The XDS110 supports alternate configurations, each of which has
a unique vid/pid:

0451/bef3 -- Standard (legacy) configuration
0451/bef4 -- Drag-n-Drop configuration
1cbe/02a5 -- CMSIS-DAP 2.0 on BULK interface configuration

It's not important to OpenOCD what the differences are except
that OpenOCD needs to know how to connect using the different
vid/pids and, in the case of the last one, use a different
interface for the debug connection.

Updated the XDS110 source to search for all possible
configurations, and updated the udev rules file to enable
user access to the alternate configuraitons.

For the curious, you can download the latest XDS emupack from
software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_software_package_download.html
Install to an empty directory, and documentation for the
XDS110 is located in the .../ccs_base/common/uscif/xds110
of the installation.

Updated for comments in code review. Changed const variable
names to lower case. Reworked interface/endpoint setting
to use arrays suggestion.

Change-Id: Icc9d11c6618f43d87ae8171c78ebf238800d3ac2
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5494
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-24 17:18:14 +00:00
Edward Fewell 87a4158acf drivers: xds110: Clean up command syntax and documentation
Arrange all commands under a top level xds110 command. Fix
documentation to properly reflect the current functionality.

Also updated the links in the document to the new permanent
links for the XDS110 only support.

Patch updated for comments from code review. Return
ERROR_COMMAND_SYNTAX_ERROR for wrong number of args in
commands. Added deprecated commands to src/jtag/startup.tcl.

Change-Id: Ica45f65e1fdf7fa72866f4e28c4f6bce428d8ac9
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5495
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-24 17:17:45 +00:00
Edward Fewell 76ba9bd0b3 tcl/target: Use sysresetreq for MSP432 targets
Confirmed that sysresetreq is supported and works better
for MSP432P4 and MSP432E4 targets than srst that was
previously being used.

Tested on MSP432P4111, MSP432P401R, and MSP432E401Y
Launchpads.

Change-Id: I1454c3379b9300bc133f82a766daeaefb98dbaac
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5488
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-24 17:17:22 +00:00
Edward Fewell c9ebd488ea drivers: xds110: Add support TCK changes in firmware update
Starting with XDS110 firmware version 3.0.0.0, the peak TCK
frequency became 14,000 kHz. So the delay count calculation
in the current driver has been updated to use the new
formula for setting the TCK speed depending on which version
of the firmware is detected. And because of the changes, the
default TCK settings for the XDS110 based Launchpads can be
adjusted to take advantage of the higher TCK performance.
Note that the values used have been determined through
testing in the automated test labs to be the highest TCK
frequency with the XDS110 that are still reliable.
Different boards have a different peak TCK setting that
should be safe.

Change-Id: I4d66e90d8fac8272641ba4db4a3a510e3b444d86
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5493
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-24 17:17:02 +00:00
Tarek BOCHKATI bff1b6f05a flash/stm32l4x: add support of STM32WB3x devices
STM32WB3x devices' flash are quite similar to STM32WB5x,
except the maximum flash size, which is 512K for WB3x and 1M for WB5x

Change-Id: I3098d7153a7429e0e72c75cec962c05768b0b018
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5475
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-23 22:09:44 +00:00
Tarek BOCHKATI c999fcef3e flash/stm32l4x: add support of STM32WLEx devices
STM32WLEx devices are based on arm Cortex-M4 running at 48MHz,
contains a single bank of maximum 256 Kbytes of flash memory.

there is 3 variants with different Flash/RAM sizes:
  STM32WLE5JC : 256K/64K
  STM32WLE5JB : 128K/48K
  STM32WLE5J8 :  64K/20K

the work-area size is set to 20 kb to fit in STM32WLE5J8

Change-Id: Ie8e186fe4be97cbc25c53ef0ade4b4dbbcee6f66
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5450
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-23 21:52:10 +00:00
Tarek BOCHKATI 4b4389a2d6 stlink: workaround serial bug with old ST-Link DFU
Old ST-LINK DFU returns an incorrect serial in the USB descriptor
 example for the following serial "57FF72067265575742132067"
  - the correct descriptor serial is:
    0x32, 0x03, 0x35, 0x00, 0x37, 0x00, 0x46, 0x00, 0x46, 0x00 ...
    this contains the length (0x32 = 50), the type (0x3 = DT_STRING)
    and the serial in unicode format.
    the serial part is: 0x0035, 0x0037, 0x0046, 0x0046 ... >>  57FF ...
    this format could be read correctly by 'libusb_get_string_descriptor_ascii'
    so this case is managed by libusb_helper::string_descriptor_equal
  - the buggy DFU is not doing any unicode conversion and returns a raw
    serial data in the descriptor:
    0x1a, 0x03, 0x57, 0x00, 0xFF, 0x00, 0x72, 0x00 ...
            >>    57          FF          72       ...
    based on the length (0x1a = 26) we could easily decide if we have to fixup the serial
    and then we have just to convert the raw data into printable characters using sprintf

example for an old ST-LINK/V2 standalone:
  before : 'W?rreWWB g'
  after  : '57FF72067265575742132067'
  => same as the displayed value in STM32CubeProgrammer

tested using these commands
  using the buggy serial
    -c "hla_serial \x57\x3f\x72\x06\x72\x65\x57\x57\x42\x13\x20\x67"
  using the computed serial
    -c "hla_serial 57FF72067265575742132067"

Change-Id: I1213818257663eeb8e76f419087d3127d0524842
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5396
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-22 08:17:14 +00:00
Tarek BOCHKATI 6ecccc8895 jtag/libusb_helper: permit adapters to compute their custom serials
introduce a callback function that could be passed to jtag_libusb_open
to permit adapters to compute their custom/exotic serials.

the callback should return a non NULL value only when the serial could not
be retrieved by the standard 'libusb_get_string_descriptor_ascii'

Change-Id: Ib95d6bdfc4ee655eda538fba8becfa183c3b0059
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5496
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-22 08:17:06 +00:00
Tarek BOCHKATI 1891c2d26e flash/stm32h7x: use proper data type (bool) for has_dual_bank
+ minor changes in comments' alignment to please our eyes

Change-Id: Ifa35a1032afc4e9aee524f596c0298a9eea49c37
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5500
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
2020-03-20 07:08:40 +00:00
Christopher Head 140fe7f714 flash/nor: check fill pattern fits in word size
Change-Id: Idad527a428ceed2b53f3da41fb0c64bf8e62614a
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5492
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2020-03-17 16:40:53 +00:00
Marc Schink aff486b6a0 rtos: Destroy RTOS and fix memory leak
The memory leak can be reproduced by using an arbitrary RTOS
and valgrind:

 $ valgrind --leak-check=full --show-leak-kinds=all

[...]
==9656== 224 (80 direct, 144 indirect) bytes in 1 blocks are definitely lost in loss record 3 of 3
==9656==    at 0x483CD99: calloc (in /usr/lib/x86_64-linux-gnu/valgrind/vgpreload_memcheck-amd64-linux.so)
==9656==    by 0x1C541A: os_alloc (rtos.c:79)
==9656==    by 0x1C569E: os_alloc_create (rtos.c:111)
==9656==    by 0x1C569E: rtos_create (rtos.c:153)
==9656==    by 0x1AE332: target_configure (target.c:4899)
==9656==    by 0x1AF228: jim_target_configure (target.c:4952)
==9656==    by 0x1C9EF9: command_unknown (command.c:1066)
==9656==    by 0x313284: JimInvokeCommand (jim.c:10364)
==9656==    by 0x313FB6: Jim_EvalObj (jim.c:10814)
==9656==    by 0x3154A3: Jim_EvalFile (jim.c:11207)
==9656==    by 0x316015: Jim_SourceCoreCommand (jim.c:15230)
==9656==    by 0x313284: JimInvokeCommand (jim.c:10364)
==9656==    by 0x313B8B: JimEvalObjList (jim.c:10605)
[...]

Change-Id: I2cd41a154fb8570842601ff4e3e76502f5908f49
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/5479
Tested-by: jenkins
Reviewed-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-17 16:40:14 +00:00
Tarek BOCHKATI dca1c6ca1f flash/startup.tcl: add STM32G0 and G4 aliases
STM32G0 and G4 uses the same flash driver as the stm32l4x

Change-Id: Ic1c4be70aaee809536912e0390f07893efb9a082
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5482
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-16 15:26:03 +00:00
Andreas Bolsch ba131f30a0 Flash driver for STM32G0xx and STM32G4xx
Flash module of STM32G0/G4 family is quite similar to the one of
STM32L4, so only minor changes are required, in particular
adaption of flash loader to Cortex-M0. Register addresses
passed to flash loader to simplify integration of L5.
Added re-probe after option byte load.
Added flash size override via cfg file.
WRPxxR mask now based on max. number of pages instead of fixed 0xFF,
as G4 devices fill up unused bits with '1'.
Sizes in stm32l4_probe changed to multiples of 1kB.

Tested with Nucleo-G071RB, G030J6, Nucleo-G431RB and Nucleo-G474RE.
Gap handling in G4 Cat. 3 dual bank mode tested with STM32G473RB.
This handling isn't optimal as the bank size includes the
size of the gap. WB not tested.

Change-Id: I24df7c065afeb71c11c7e96de4aa9fdb91845593
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4807
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-16 15:25:10 +00:00
Marek Vasut e03de33c41 tcl/target: Fix naming of RZ/A1 SoC
The RZ/A1 is not part of the R-Car family, but is rather an RZ family.
Fix the naming.

Change-Id: I5f882b2467e87e534e0f1c827554e664a7d55664
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5445
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-14 20:39:47 +00:00
Edward Fewell a34c336cbf drivers: xds110: Fix errors in routine that toggles
TCK during nSRST assert/deassert code.

To support LPRF targets (CC13xx/CC26xx), TCK must be toggled
for 50 ms while nSRST is asserted and right after it is
released. This allows the core to halt in boot ROM before
code is run that might interfere with debug access.

The current routine has two issues. It shouldn't be run at
all if the target is using SWD. And the delay needs to
be a real-time 50 ms, so the number of TCK periods should
be calculated off the set speed.

Change-Id: If993031b84cf2a505ea67a6633602c4b01cd8e1e
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5497
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-14 19:16:42 +00:00
Antonio Borneo b5d2b1224f target/cortex_a: add hypervisor mode
Hypervisor mode is present only if the optional virtualization
extensions are available. Moreover, virtualization extensions
require that also security extensions are implemented.

Add the required infrastructure for the shadowed registers in
hypervisor mode.
Make monitor shadowed registers visible in hypervisor mode too.
Make hypervisor shadowed registers visible in hypervisor mode
only.
Check during cortex_a examine if virtualization extensions are
present and then conditionally enable the visibility of both
hypervisor and monitor modes shadowed registers.

Change-Id: I81dbb1ee8baf4c9f1a2226b77c10c8a2a7b34871
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5261
Tested-by: jenkins
2020-03-12 10:11:19 +00:00
Antonio Borneo 6900c5af4e armv7a: access monitor registers only with security extensions
Accordingly to ARM DDI 0406C at B1.5, the security extensions for
armv7a are optional extensions and can be detected by reading
ID_PFR1.
The monitor mode is part of the security extensions and the shadow
registers "sp_mon", "lr_mon" and "spsr_mon" are only present with
the security extensions.

Read the register ID_PFR1 during cortex_a examine, determine if
security extension is present and then conditionally enable the
visibility of the monitor mode shadow registers.

Change-Id: Ib4834698659046566f6dc5cd35b44de122dc02e5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5259
Tested-by: jenkins
2020-03-12 10:10:33 +00:00
Antonio Borneo 9626402c5a target/armv4_5: remove unused macro
The macro ARMV4_5_CORE_REG_MODENUM() is unused.
Remove it!

Change-Id: I183df57bd86c9428710ea3583e43fba88fd26e0a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5260
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org>
2020-03-12 10:09:15 +00:00
Antonio Borneo fba438fde7 arm: Use different enum for core_type and core_mode
The fields core_type and core_mode use the same enum arm_mode
but encode different information, making the code less immediate
to read.

Use a different enum arm_core_type for the field core_type.
The code behavior is not changed.

Change-Id: I60f2095ea6801dfe22f6da81ec295ca71ef90466
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5258
Tested-by: jenkins
2020-03-12 10:05:42 +00:00
Antonio Borneo f447c31b30 arm: fix reg num for Monitor mode
Commit 2efb1f14f6 ("Add GDB remote target description support
for ARM4") inserts two additional registers "sp" and "lr" in the
table arm_core_regs[], thus shifting by two the position of the
last three registers already present
	"sp_mon" moved from index 37 to 39
	"lr_mon" moved from index 38 to 40
	"spsr_mon" moved from index 39 to 41
Part of the code is updated (e.g. enum defining ARM_SPSR_MON and
array arm_mon_indices[]), but it's missing the update of mapping
in armv4_5_core_reg_map[].

Fix armv4_5_core_reg_map[].

Change-Id: I0bdf766183392eb738206b876cd9559aacc29fa0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 2efb1f14f6 ("Add GDB remote target description support for ARM4")
Reviewed-on: http://openocd.zylin.com/5257
Tested-by: jenkins
2020-03-12 10:05:30 +00:00
Antonio Borneo fbbfbb2516 ftdi: flush mpsse queue after a level change on reset pins
The function ftdi_set_signal() does not propagate the pin change
until next call to mpsse_flush(). Current code does not toggles
immediately the reset pins if polling is turned off.

Call mpsse_flush() at the end of ftdi_reset().
While there, remove the duplicated LOG message.

Change-Id: I79eacfe4fc32b5cdf2dc1b78f3660d96988466bc
Fixes: 8850eb8f2c ("swd: get rid of jtag queue to assert/deassert srst")
Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5431
Tested-by: jenkins
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-12 10:05:09 +00:00
Antonio Borneo 2e1dfebc8e jimtcl: update to tag 0.79
OpenOCD is stuck at jimtcl tag 0.77 that is 3 years old.
The latest tag 0.79 (2019-11-20) is already used by debian build,
which packs jim library separately, as shown in [1]. Today only
the build for architecture powerpcspe is still not updated to
latest package version.
I have been using jim 0.79 since the day of the release, without
any issue.

Switch jimtcl to latest tag 0.79

[1] https://packages.debian.org/sid/openocd

Change-Id: I3426e68c32f88ecde74d4278303925423db451e0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5403
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-12 10:04:25 +00:00
Antonio Borneo 939febecca target: fix crash with jimtcl 0.78
The jimtcl commit 41c5ff1809f5 ("jim.c: Fix Object leak in zlib
support") https://repo.or.cz/jimtcl.git/commit/41c5ff1809f5
makes Jim_SetResultFormatted() freeing the parameters that have
zero refcount.

OpenOCD commit 559d08c19e ("jim tests: use installed") adds the
only code instance in OpenOCD that first passes a zero refcount
object to Jim_SetResultFormatted() and then frees it.
By switching jimtcl version to 0.78 or newer this causes a crash
of OpenOCD.
To trigger the crash in a telnet session, check that the current
target is running and type:
	[target current] arp_waitstate halted 1

Remove the call to Jim_FreeNewObj() after the call to
Jim_SetResultFormatted().

Change-Id: I5f5a8bca96a0e8466ff7b789fe578ea9785fa550
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5453
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-12 10:03:57 +00:00
Antonio Borneo 44967a9e07 jtag: report API reset as synchronous
The jtag API reset() is synchronous, but this was not highlighted
in the description.

Change-Id: I76ffb7eec97c8608cfbef0b9268ee18a5f50b221
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 8850eb8f2c ("swd: get rid of jtag queue to assert/deassert srst")
Reviewed-on: http://openocd.zylin.com/5471
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
2020-03-12 10:03:42 +00:00
Tarek BOCHKATI 221fe49879 semihosting: add semihosting handlers to AArch64
note: this works only when the PE is in AArch64 state

Change-Id: Id6a336ca7d201df72bd1aaaeccce4185473fc1bd
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5474
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-12 09:48:56 +00:00
Matthias Welwarsky afe899f938 cortex_a: warn on broken debug_base setting
A common problem with target configurations appears to be broken
debug base address configuration. ARM DDI0406C.d specifies in App. D,
1.4.1, that bit 31 of the debug base address serves as identification
of an external debugger, as opposed to an internal access to memory
mapped debug registers by the CPU. External accesses are treated
as privileged and require no debug authentification via the lock
access register.

Sometimes the base address of a debug component is wrong even
in the targets' ROM table. In this case, the correct base address
must be specified using the -dbgbase argument when creating the
target.

This patch adds a warning when bit 31 of the debug base address
is not set, as a hint to the user.

Change-Id: I9c41d85a138123c657ef655e3436a2aa39249dcc
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/5105
Tested-by: jenkins
Reviewed-by: Tommy Vestermark <tov@vestermark.dk>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-12 09:48:25 +00:00
Tarek BOCHKATI a8b1bd8376 target/armv8_opcodes: use T32 instructions when the PE is in AArch32 state
As stated in ARM v8-A Architecture Reference Manual (ARM DDI 0487E.a)
in Chapter H4.3 DCC and ITR access modes:
    Writes to EDITR trigger the instruction to be executed if the PE
    is in Debug state:
      - If the PE is in AArch64 state, this is an A64 instruction.
      - If the PE is in AArch32 state, this is a T32 instruction

But in armv8_opcodes specifically in t32_opcodes we were using some
A32 instructions for HLT, LDRx and STRx opcodes.

Using the correct LDRx and STRx opcodes, fixes 16 and 8 bits memory access
when the PE is in AArch32 state.

Change-Id: Ib1acbdd4966297e7b069569bcb8deea3c3993615
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5346
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-12 09:47:08 +00:00
Tarek BOCHKATI a154973896 target/aarch64: fix soft breakpoint when PE is in AArch32 state
Before this patch aarch64_set_breakpoint was using either A64, or A32
HLT opcode by relying on armv8_opcode helper.
This behaviors ignores the fact that in AArch32 state the core could
execute Thumb-2 instructions, and gdb could request to insert a soft
bkpt in a Thumb-2 code chunk.

In this change, we check the core_state and bkpt length to know the
correct opcode to use.

Note: based on https://sourceware.org/gdb/current/onlinedocs/gdb/ARM-Breakpoint-Kinds.html
      if bkpt length/kind == 3, we should replace a 32-bit Thumb-2 opcode,
      then we use twice the 16 bits Thumb-2 bkpt opcode and we fix-up the
      length to 4 bytes, in order to set correctly the bpkt.

Change-Id: I8f3551124412c61d155eae87761767e9937f917d
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5355
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-12 09:46:43 +00:00
Tarek BOCHKATI 4845b54372 target/aarch64: fix minor stepping issue with gdb
when using step command from gdb the step happens without any issue,
but aarch64_step call explicitly aarch64_poll which consumes the
status change to HALTED, so it does not inform gdb that the step has
finished.

by removing this call, all is back to normal and openocd could inform gdb
that the step has finished.

Change-Id: I9366aecd20f7d52259b050b8653189b67d9299d0
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5354
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-12 09:45:36 +00:00
Tomas Vanek 9f4659ae6b target: add examine-fail event
A configuration script may want to check the reason why examine fails
e.g. device has security lock engaged.

tcl/target/kx.cfg and klx.cfg is modified to use the new event
for testing of the security lock of Kinetis MCU

Change-Id: Id1d3a79d24e84b513f4ea35586cd2ab0437ff9b3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4289
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-12 09:43:55 +00:00
Anton V. Kirilchik 69f0105324 Add target config for STM8S103 chip...
Change-Id: I693e5b7933fc61956010a96be57ee6eb8abd3c31
Signed-off-by: Anton V. Kirilchik <kosmonaffft@gmail.com>
Reviewed-on: http://openocd.zylin.com/5422
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-12 09:41:41 +00:00
Tarek BOCHKATI a99bf2ea94 semihosting: reorganize semihosting commands
the same semihosting handlers chain is declared twice:
 1. in src/target/armv4_5.c
 2. in src/target/riscv/riscv.c

to make it simpler we moved the declaration into
'src/target/semihosting_common.c' under semihosting_common_handlers[].
then we used this into both of armv4_5.c and riscv.c

Change-Id: If813b3fd5eb2476658f1308f741c4e805141f617
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5473
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org>
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Liviu Ionescu <ilg@livius.net>
2020-03-10 20:20:22 +00:00
Tarek BOCHKATI 123e10288d flash/stm32h7x: fix bank sizes for devices with trimmed flash
STM32H7yxxI: dual independent 1 MByte banks
STM32H7yxxG: dual independent 512 Kbyte banks
STM32H7yxxB: single 128 Kbyte bank

where y = [4/5] or [A/B]

references: (documents are available in www.st.com)
 - STM32H7[4/5]x[G/I] : DS12110 Rev 7
    >> 3.3.1 Embedded Flash memory
 - STM32H750xB : RM0433 Rev 6
    >> Table 11. Flash memory organization on STM32H750xB devices
 - STM32H7[A/B]x[B/G/I] : RM0455 Rev 3
    >> 4.3.4 Flash memory architecture and usage


Change-Id: Ic9346964ef2554abf47f5832e25adfdc77bd323e
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5442
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
2020-03-10 20:18:47 +00:00
Marek Vasut b304971f38 tcl/target: Unify Renesas R-Car JTAG reset config
Both Gen2 and Gen3 used the same init_reset{} implementation,
pull it into common file and include it from both generations.
Moreover, this behavior is SoC specific, not board specific,
so move the common init_reset into target/ directory.

Change-Id: I5489a4bff9a786da8cb7fd7a515b0c9ce9dc16e3
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5400
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-09 05:59:39 +00:00
Edward Fewell 82a5c55dc3 flash/nor: update support for TI MSP432 devices
Added fixes for issues found in additional code reviews.

Fixed host Endianness issues with using buffer reads
and writes instead of the *_u32 variants.

Changed code that tried to ID banks by hardcode
bank_number values to use instead the bank base
address. This fixes problems using configurations
with multiple devices.

Note that this replaces Change 4786 which has
been abandoned because of extensive changes to
the code to stop IDing banks by name.  And I
think I really messed up a rebase/merge on the
document file.

Tested on MSP432P401R, MSP432P4111, and MSP432E401Y
Launchpads.

Change-Id: Id05798b3aa78ae5cbe725ee762a164d673ee5767
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5481
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-07 15:32:24 +00:00
luca vinci e9932ef23d bluenrg-x: simplyfied the driver
Adopted only fast algorithm for flash programming:
- write_word and write_byte methods have been removed.
- start and end write alignments have been defined.
Moved flash controller registers offsets in a common file
shared with the flash algorithm.
- the flash base address is passed to the flash algorithm
  as a parameter.
Removed unused functions

Change-Id: I80aeab3994e477044bbcf02e66d9525dae0cb491
Signed-off-by: luca vinci <luca.vinci@st.com>
Reviewed-on: http://openocd.zylin.com/5393
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Michele Sardo <msmttchr@gmail.com>
2020-03-07 15:31:09 +00:00
luca vinci 6bc0a77a6e bluenrg-x: added support for BlueNRG-LP device
Extended bluenrg-x flash driver with BlueNRG-LP flash controller.
Changes include:
- register set for the flash controller
- made software structure prone to support more easily future devices
- updated target config file

Change-Id: I2e2dc70db32cf98c62e3a43f2e44a4600a25ac5b
Signed-off-by: luca vinci <luca.vinci@st.com>
Reviewed-on: http://openocd.zylin.com/5343
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-07 15:31:02 +00:00
Tomas Vanek a2e822834d helper/binarybuffer: fix clang static analyzer warnings
Writing bits to an uninitialized buffer generated false warnings.
Zero buffers before setting them by buf_set_u32|64()
(do it only if bit-by-bit copy loop is used,
zeroed buffer is not necessary if a fast path write is used)

Change-Id: I2f7f8ddb45b0cbd08d3e249534fc51f4b5cc6694
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5383
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-03-07 15:30:05 +00:00
Tomas Vanek 4e981bc27c target/arm920t: fix clang static analyzer warning
Change-Id: I570dfb8b20a3f187f1fe660343cf0b75691e2c30
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5375
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-07 15:29:44 +00:00