Make driver_priv point directly into the corresponding chip bank structure
and add a pointer to it to get back to its chip when it's needed. This
removes the need to keep track of any bank number, either global or chip-
local.
In addition, it simplifies the cases where the chip structure was just used
to access the chip bank fields; now they are directly accessible.
Change-Id: Iaa353cd4fa7d8ff94c2ef69028c7cb32fade0420
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/4775
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The current code checks the count to determine whether to read bytes or
words. However it fails to consider whether the base address is suitably
aligned.
Instead use the target_read_buffer() function which is for exactly this
purpose and generates optimal accesses with natural alignment.
Change-Id: I32ab5417890ee2219902df1529bc220fe353b4c7
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3217
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The preverify option allows to check whether flashing is necessary.
If the target is flashed often/automatically this can save time and
preserve the flash. This is expecially helpful in CI environments.
Change-Id: Iead0a269e1a772b751d4dd9e8b53b2fecc874624
Signed-off-by: Moritz 'Morty' Strübe <moritz.struebe@redheads.de>
Reviewed-on: http://openocd.zylin.com/5292
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
I think that libusb_handle_events_timeout_completed is supposed to make
progress or time out, but sometimes we hit a case where it makes no
progress, and mpsse_flush() loops forever. This wall clock timeout
notifies the user that this is going on.
When I wrote this code, this bug would reproduce every hour or two, but
right now it's not happening for me.
Change-Id: I7eb66f43462298e263a48048aa0c8769095661eb
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4767
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This makes behavior when you've configured an SMP group of heterogeneous
targets a bit less weird. (You still shouldn't be doing that, since gdb
and who knows what else assumes that the targets in an SMP group are
homogeneous.)
Specifically, if you have a HiFive Unleashed board (where the first core
is fairly basic and the other 4 or more full-featured) this lets you
connect to all 5, and still have access to the FPU etc. on the higher
numbered cores.
Change-Id: I2e01f63f8753f78c29d7f414ea603e02bf0390e0
According to the reference manual it should be 0x40000000. Flashing (and
booting) a firmware with this MSC base was successful.
Change-Id: I739e67d36555b8170a3b8e26f54cf1c09ce8424b
Signed-off-by: Christian Meusel <christian.meusel@posteo.de>
Reviewed-on: http://openocd.zylin.com/5263
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Also change the address that we use to link the PIC code, so that if
there is a PIC issue in the future it will show up on hardware I test
against.
Also remove fespi.S, which hasn't been used in a long time.
Change-Id: I667d930b48107a3522d619167c7afc335431b4b6
* Add riscv_batch_available_scans().
This function will query the number of available scans in a batch.
* Perform SBA writes with batch transactions for improved performance.
Using batch transactions avoids an unnecessary dmi read after every
dmi write, resulting in a significant performance improvement.
Fix expression "(pin_status | 0x4)" which was always true rather than
testing a bit. Untested - was clearly not expressing the intent of the
author by inspection. Found by automated tooling and rtrieu@google.com.
Signed-off-by: Seth LaForge <sethml@google.com>
Change-Id: I4bb91e60e8ce9757bf21976cc48de6f85a39c68d
Reviewed-on: http://openocd.zylin.com/5301
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The C standard says that errno is set to ERANGE if an out-of-range value
is returned by strtol, strtoul, et. al., but it does not say that errno
is cleared if the function is successful (and, indeed, it is not on
glibc). This means that, if errno is ERANGE before strtol is called, and
if the value to be converted is exactly the maximum (or, for a signed
conversion, the minimum) legal value, COMMAND_PARSE_NUMBER will
erroneously indicate that the value is out of range.
Change-Id: I8a8b50a815b408a38235968f1c1d70297ea1a6aa
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5298
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
PAGE_SIZE is defined in system includes on some systems, this would
avoid the unintended conflict
Fixes
| src/flash/nor/esirisc_flash.c:95:9: error: 'PAGE_SIZE' macro redefined [-Werror,-Wmacro-redefined]
| #define PAGE_SIZE 4096
| ^
| /mnt/a/yoe/build/tmp/work/core2-64-yoe-linux-musl/openocd/0.10+gitrAUTOINC+7ee618692f-r0/recipe-sysroot/usr/inclu
de/limits.h:89:9: note: previous definition is here
| #define PAGE_SIZE PAGESIZE
Change-Id: I195b303fc88a7c848ca4e55fd6ba893796df55cc
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Reviewed-on: http://openocd.zylin.com/5180
Tested-by: jenkins
Reviewed-by: Steven Stallion <sstallion@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
* Align algorithm stack to XLEN.
This fixes algorithm timeout on RV64 targets.
Also improve debug information in various places.
Change-Id: Id3121f9c6e753c6a7e14da511e4de0587a6f7b4d
* Compile 32-bit RISC-V algorithms for RV32E.
Change-Id: I33a698c0c6ba540de29fa0459242c72a67b0cbaa
* Remove debug code.
Change-Id: I37c966ce0f2d1fe68cd6ae0724d19ae95ebaf51b
* Dump start of gdb packets escaping non-printable.
Change-Id: Ie5f36b5c9041bfc0e5aa9543f0afe2c4810c2915
* Propagate flash programming errors.
Change-Id: I0c938ce7a1062bcc93426538cbc82424000f37b7
* Improve debug messaging.
Change-Id: I47ac3518f3b241986c677824864102936100adf6
* Add debug output to flash image.
This is helpful when you're debugging the flash algorithm itself, and a
nop when running it through OpenOCD.
Change-Id: Id44c6498c288872cc2cec79044116ac38198c572
* Make timeout depend on how much data is written.
Change-Id: I819efa04cd6f6bd6664afd5c53cc7a8a5c84f54e
* Fix issi erase commands.
This is required to flash HiFive Unleashed.
Change-Id: I33e4869d1d05ca8a1df6136bccf11afda61bfe10
* Fix running algorithm on multicore `-rtos riscv`.
The bug was that poll() might change the currently selected hart, and in
that case we'd access registers on that other hart after the algorithm
is finished.
Change-Id: I140431898285cf471b372139cef2378ab4879377
* Make fespi flash algorithm debugging optional.
Also add a scheme that allows you to see the stack trace of where a
failure occurred if debugging is enabled.
Change-Id: Ia9a3a9a941ceba0f8ff6b47da5a8643e5f84b252
There is no sense in displaying the max size (2M) as there is variants
of this device with reduced flash size
Change-Id: I40574064d75fdf2a038044c81038a6d7abc6c4dd
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5288
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
SWM050 is a series of MCU product by Foshan Synwit Tech, which is
available in TSSOP-8 or SSOP-16 packages.
Adds flash driver for the internal 8KiB flash of the MCU. The registers
are based on reverse engineering the J-Flash blob provided by the
vendor.
Also adds a pre-made cfg file.
Change-Id: I0b29f0c0d062883542ee743e0750a4c6b6609ebd
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Caleb Szalacinski <contact@skiboy.net>
Reviewed-on: http://openocd.zylin.com/4927
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Added "exist=true" field to the reg_list struct to make access to the
dsp563xx registers again possible. Without it defaults to exist=false
and all the reg related functions will return nothing.
Fixes regression from b5964191f0
Change-Id: I9c256346735b8d66919c4ba83f528a8afca46ff9
Signed-off-by: Han Hartgers <han.hartgers@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5239
Tested-by: jenkins
Fix two expressions where precedence of operator | vs ?: was clearly confused.
Untested - was clearly not expressing the intent of the author by inspection.
Found by automated tooling and rtrieu@google.com.
Change-Id: I46f190154797f8affc761caf3a15a1a9db53d702
Signed-off-by: Seth LaForge <sethml@google.com>
Reviewed-on: http://openocd.zylin.com/5281
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
1. Add get_thread_reg() to rtos. It's used in rtos_get_gdb_reg() to read
the value of a single register, instead of reading all register values
by calling get_thread_reg_list().
2. Add set_reg() to rtos. gdb_server uses this to change a single
register value for a specific thread.
3. Add target_get_gdb_reg_list_noread() so it's possible for gdb to get
a list of registers without attempting to read their contents.
The clang static checker doesn't find any new problems with this change.
Change-Id: I77f792d1238cb015b91527ca8cb99593ccc8870e
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/5114
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
* Clear cmderr by writing all ones.
This should have been part of #389.
Change-Id: Ie40e95fdd904af65c53d1f5de7c8464b27038ec0
* Don't update reg cache in register_write_direct().
This function explicitly bypasses any caches.
Change-Id: Ie3c9a1163e870f80c0ed75b74495079c527663e9
* Use only one hart to run algorithm.
Fixes a bug with `-rtos hwthread` where all harts would run when running
a flash/CRC algorithm, which would probably ruin flashing, and was
unexpectedly changing registers on other harts for the CRC algorithm.
Change-Id: Ia2f600624f4c8d4cab319861fef2c14722f08b53
* Adds support for RISCV Access Memory Abstract Commands
The Access Memory Abstract Command is one of the three optional
methods for reading and writing memory on a complient RISCV
debug module. The previous two options were already implemented
in OpenOCD.
Implementation Notes:
- aamvirtual is hard-coded to false until the design for accessing
virtual addresses is finalized.
- aamsizes corresponding to 8b, 16b, 32b, and 64b are supported.
128b support is postponed until it is required, as it will mean
changes to the read/write_abstract_arg() interface to pass 128b
values.
- aampostincrement is not used and hard-coded to false.
* Changes from review.
* Additional lint fixes and a typo from last commit.
* Fixing a clang error.
* Fixes a last-minute change that broke writes with width > 8b.
* Removing memcpy after adding read_from_buf().
Fake step is a hack introduced to make things work with real RTOSs that
have a concept of a current thread. The hwthread rtos always has access
to all threads, so doesn't need it.
This fixes a bug when running my MulticoreRegTest against HiFive
Unleashed where OpenOCD would return the registers of the wrong thread
after gdb stepped a hart.
Change-Id: I64f538a133fb078c05a0c6b8121388b0b9d7f1b8
This is causing repeated build failures. Its design is so fundamentally
broken that if someone actually wants to use it, a full rewrite is the
only option. So it's not even worth deprecating in the hope that someone
will notice and fix it, just get rid of it.
Change-Id: I513069919a3873bd69253110f7fb6f622ee7d061
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/5243
Tested-by: jenkins
Reviewed-by: Jeffrey Booher-Kaeding <Jeff.Booher-Kaeding@arm.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* add opcode for csrrsi and csrrci
* enable MMU while reading/writing memory using progbuf
* fix style issues
* keep old behavior for progbufsize<4, perform r/w/csr only when necessary
* do not pass progbufsize, only write mstatus if changed
* add config option to enable virtualization feature
* throw error if virt enabled but unavaliable, outsource modify_privilege
* support virtualization for read_memory_progbuf_one
gdb has developed a nasty habit of very often reading 30-some
half-words. This change speeds that up significantly.
Change-Id: Iab1b7575bec5c57051c6e630ae292dddf8fe6350
* Make resume order configurable.
This is a customer requirement. Using this option is discouraged.
Change-Id: I520ec19cc23d7837cb8576f69dadf2b922fa2628
* Fix style.
Change-Id: If8e515984c92ce8df52aa69e87abde023897409f
* Make mingw32-gcc happy.
Change-Id: I39852aedec293294b2b2638ab2cc45494fe77beb
* WIP, rewrite of flash algorithm.
Just put all the flashing logic into the algorithm, instead of using an
intermediate format. This should reduce total data written while
flashing by about 9%, and also makes the code much simpler.
Change-Id: I807e60c8ab4f9f376cceaecdbbd10a2326be1c79
* New algorithm works.
Speeds up Arty flashing another 9%.
wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 86.784538s (25.074 KiB/s)
verified 2192012 bytes in 6.693336s (319.816 KiB/s)
8.66user 13.03system 1:33.91elapsed 23%CPU (0avgtext+0avgdata 12272maxresident)k
Change-Id: Ie55c5250d667251be141cb32b144bbcf3713fce4
* Fix whitespace.
Change-Id: I338d518fa11a108efb530ffe75a2030619457a0b
* Don't reserve so much stack space.
Also properly check XLEN in riscv_wrapper.S.
Change-Id: Ifa0301f3ea80f648fb8a6d6b6c8bf39f386fe4a6
Andreas Fritiofson
Andreas Färber
Felipe Balbi
Al Dyrius
Moritz 'Morty' Strübe
Tomas Vanek
Tim Newsome
Christian Meusel
darius-bluespec
Seth LaForge
Christopher Head
Marc Schink
Khem Raj
Greg Savin
Tarek BOCHKATI
Caleb Szalacinski
Han Hartgers
dave-estes-syzexion
Nils Wistoff