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MemTest64 passes. 

Change-Id: I75996b71c3f31025c89ef596a08e01d191405336
This commit is contained in:
Tim Newsome 2017-10-17 11:15:51 -07:00
parent d94b38279a
commit fbe2980eb7
2 changed files with 18 additions and 4 deletions
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3
src/target/riscv/batch.c
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@ -49,13 +49,12 @@ void riscv_batch_run(struct riscv_batch *batch)
return; return;
} }
keep_alive(); keep_alive();
LOG_DEBUG("running a batch of %ld scans", (long)batch->used_scans); LOG_DEBUG("running a batch of %ld scans", (long)batch->used_scans);
riscv_batch_add_nop(batch); riscv_batch_add_nop(batch);
for (size_t i = 0; i < batch->used_scans; ++i) { for (size_t i = 0; i < batch->used_scans; ++i) {
dump_field(batch->fields + i);
jtag_add_dr_scan(batch->target->tap, 1, batch->fields + i, TAP_IDLE); jtag_add_dr_scan(batch->target->tap, 1, batch->fields + i, TAP_IDLE);
if (batch->idle_count > 0) if (batch->idle_count > 0)
jtag_add_runtest(batch->idle_count, TAP_IDLE); jtag_add_runtest(batch->idle_count, TAP_IDLE);

19
src/target/riscv/riscv-013.c
View File

@ -1316,6 +1316,7 @@ static int read_memory(struct target *target, target_addr_t address,
AC_ACCESS_REGISTER_TRANSFER | AC_ACCESS_REGISTER_TRANSFER |
AC_ACCESS_REGISTER_POSTEXEC)) != ERROR_OK) AC_ACCESS_REGISTER_POSTEXEC)) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
// First read has just triggered. Result is in s1.
dmi_write(target, DMI_ABSTRACTAUTO, dmi_write(target, DMI_ABSTRACTAUTO,
1 << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET); 1 << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET);
@ -1329,6 +1330,7 @@ static int read_memory(struct target *target, target_addr_t address,
// Invariant: // Invariant:
// s0 contains the next address to read // s0 contains the next address to read
// s1 contains the data read at the previous address // s1 contains the data read at the previous address
// dmdata0 contains the data read at the previous previous address
unsigned start = (cur_addr - address) / size; unsigned start = (cur_addr - address) / size;
LOG_DEBUG("creating burst to read address 0x%" TARGET_PRIxADDR LOG_DEBUG("creating burst to read address 0x%" TARGET_PRIxADDR
@ -1385,7 +1387,10 @@ static int read_memory(struct target *target, target_addr_t address,
// Now read whatever we got out of the batch. // Now read whatever we got out of the batch.
unsigned rereads = 0; unsigned rereads = 0;
for (riscv_addr_t addr = cur_addr; addr < next_addr; addr += size) { for (riscv_addr_t addr = cur_addr - size; addr < next_addr - size; addr += size) {
if (addr < address)
continue;
riscv_addr_t offset = addr - address; riscv_addr_t offset = addr - address;
uint64_t dmi_out = riscv_batch_get_dmi_read(batch, rereads); uint64_t dmi_out = riscv_batch_get_dmi_read(batch, rereads);
@ -1403,6 +1408,14 @@ static int read_memory(struct target *target, target_addr_t address,
dmi_write(target, DMI_ABSTRACTAUTO, 0); dmi_write(target, DMI_ABSTRACTAUTO, 0);
if (count > 1) {
// Read the penultimate word.
uint64_t value = dmi_read(target, DMI_DATA0);
write_to_buf(buffer + cur_addr - size - address, value, size);
LOG_DEBUG("M[0x%" TARGET_PRIxADDR "] reads 0x%" PRIx64, cur_addr -
size, value);
}
// Read the last word. // Read the last word.
uint64_t value; uint64_t value;
if (register_read_direct(target, &value, GDB_REGNO_S1) != ERROR_OK) if (register_read_direct(target, &value, GDB_REGNO_S1) != ERROR_OK)
@ -1508,7 +1521,7 @@ static int write_memory(struct target *target, target_addr_t address,
// Write value. // Write value.
dmi_write(target, DMI_DATA0, value); dmi_write(target, DMI_DATA0, value);
// Write and execute command that moves value into S0 and // Write and execute command that moves value into S1 and
// executes program buffer. // executes program buffer.
uint32_t command = access_register_command(GDB_REGNO_S1, 32, uint32_t command = access_register_command(GDB_REGNO_S1, 32,
AC_ACCESS_REGISTER_POSTEXEC | AC_ACCESS_REGISTER_POSTEXEC |
@ -1521,6 +1534,8 @@ static int write_memory(struct target *target, target_addr_t address,
// Turn on autoexec // Turn on autoexec
dmi_write(target, DMI_ABSTRACTAUTO, dmi_write(target, DMI_ABSTRACTAUTO,
1 << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET); 1 << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET);
setup_needed = false;
} else { } else {
riscv_batch_add_dmi_write(batch, DMI_DATA0, value); riscv_batch_add_dmi_write(batch, DMI_DATA0, value);
if (riscv_batch_full(batch)) if (riscv_batch_full(batch))