Merge branch 'dsp5680xx_cherry' of git://repo.or.cz/openocd/dsp568013 into fix
This commit is contained in:
Øyvind Harboe
commit
fbbce95140
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@ -157,7 +157,7 @@ static int dsp5680xx_flash_write(struct flash_bank *bank, uint8_t *buffer, uint3
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LOG_ERROR("%s: Writing to odd addresses not supported. This chip uses word addressing, Openocd only supports byte addressing. The workaround results in disabling writing to odd byte addresses.",__FUNCTION__);
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return ERROR_FAIL;
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}
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retval = dsp5680xx_f_wr(bank->target, buffer, bank->base + offset/2, count);
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retval = dsp5680xx_f_wr(bank->target, buffer, bank->base + offset/2, count, 0);
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uint32_t addr_word;
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for(addr_word = bank->base + offset/2;addr_word<count/2;addr_word+=(HFM_SECTOR_SIZE/2)){
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if(retval == ERROR_OK)
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@ -90,12 +90,17 @@ static int dsp5680xx_irscan(struct target * target, uint32_t * data_to_shift_int
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err_check(retval,"Invalid tap");
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}
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if (ir_len != target->tap->ir_length){
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LOG_WARNING("%s: Invalid ir_len of core tap. If you are removing protection on flash then do not worry about this warninig.",__FUNCTION__);
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//return ERROR_FAIL;//TODO this was commented out to enable unlocking using the master tap. did not find a way to enable the master tap without using tcl.
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if(target->tap->enabled){
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retval = ERROR_FAIL;
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err_check(retval,"Invalid irlen");
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}else{
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struct jtag_tap * master_tap = jtag_tap_by_string("dsp568013.chp");
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if((master_tap == NULL) || ((master_tap->enabled) && (ir_len != DSP5680XX_JTAG_MASTER_TAP_IRLEN))){
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retval = ERROR_FAIL;
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err_check(retval,"Invalid irlen");
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}
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}
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}
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//TODO what values of len are valid for jtag_add_plain_ir_scan?
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//can i send as many bits as i want?
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//is the casting necessary?
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jtag_add_plain_ir_scan(ir_len,(uint8_t *)data_to_shift_into_ir,(uint8_t *)data_shifted_out_of_ir, TAP_IDLE);
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if(dsp5680xx_context.flush){
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retval = dsp5680xx_execute_queue();
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@ -445,6 +450,52 @@ static int eonce_exit_debug_mode(struct target * target,uint8_t * eonce_status){
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return retval;
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}
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int switch_tap(struct target * target, struct jtag_tap * master_tap,struct jtag_tap * core_tap){
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int retval = ERROR_OK;
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uint32_t instr;
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uint32_t ir_out;//not used, just to make jtag happy.
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if(master_tap == NULL){
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master_tap = jtag_tap_by_string("dsp568013.chp");
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if(master_tap == NULL){
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retval = ERROR_FAIL;
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err_check(retval,"Failed to get master tap.");
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}
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}
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if(core_tap == NULL){
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core_tap = jtag_tap_by_string("dsp568013.cpu");
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if(core_tap == NULL){
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retval = ERROR_FAIL;
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err_check(retval,"Failed to get core tap.");
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}
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}
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if(!(((int)master_tap->enabled) ^ ((int)core_tap->enabled))){
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LOG_WARNING("Wrong tap enabled/disabled status:\nMaster tap:%d\nCore Tap:%d\nOnly one tap should be enabled at a given time.\n",(int)master_tap->enabled,(int)core_tap->enabled);
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}
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if(master_tap->enabled){
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instr = 0x5;
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retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_MASTER_TAP_IRLEN);
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err_check_propagate(retval);
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instr = 0x2;
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retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & ir_out,4);
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err_check_propagate(retval);
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core_tap->enabled = true;
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master_tap->enabled = false;
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}else{
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instr = 0x08;
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retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
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err_check_propagate(retval);
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instr = 0x1;
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retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & ir_out,4);
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err_check_propagate(retval);
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core_tap->enabled = false;
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master_tap->enabled = true;
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}
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return retval;
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}
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#define TIME_DIV_FREESCALE 0.3
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/**
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* Puts the core into debug mode, enabling the EOnCE module.
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*
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@ -454,6 +505,108 @@ static int eonce_exit_debug_mode(struct target * target,uint8_t * eonce_status){
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* @return
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*/
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static int eonce_enter_debug_mode(struct target * target, uint16_t * eonce_status){
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int retval = ERROR_OK;
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uint32_t instr = JTAG_INSTR_DEBUG_REQUEST;
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uint32_t ir_out;//not used, just to make jtag happy.
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uint16_t instr_16;
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uint16_t read_16;
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struct jtag_tap * tap_chp;
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struct jtag_tap * tap_cpu;
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tap_chp = jtag_tap_by_string("dsp568013.chp");
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if(tap_chp == NULL){
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retval = ERROR_FAIL;
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err_check(retval,"Failed to get master tap.");
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}
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tap_cpu = jtag_tap_by_string("dsp568013.cpu");
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if(tap_cpu == NULL){
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retval = ERROR_FAIL;
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err_check(retval,"Failed to get master tap.");
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}
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// Enable master tap
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tap_chp->enabled = true;
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tap_cpu->enabled = false;
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instr = MASTER_TAP_CMD_IDCODE;
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retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_MASTER_TAP_IRLEN);
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err_check_propagate(retval);
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usleep(TIME_DIV_FREESCALE*100*1000);
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// Enable EOnCE module
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jtag_add_reset(0,1);
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usleep(TIME_DIV_FREESCALE*200*1000);
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instr = 0x0606ffff;// This was selected experimentally.
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retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & ir_out,32);
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err_check_propagate(retval);
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// ir_out now hold tap idcode
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// Enable core tap
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tap_chp->enabled = true;
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retval = switch_tap(target,tap_chp,tap_cpu);
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err_check_propagate(retval);
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instr = JTAG_INSTR_ENABLE_ONCE;
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//Two rounds of jtag 0x6 (enable eonce) to enable EOnCE.
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retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
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err_check_propagate(retval);
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instr = JTAG_INSTR_DEBUG_REQUEST;
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retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
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err_check_propagate(retval);
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instr_16 = 0x1;
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retval = dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,8);
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instr_16 = 0x20;
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retval = dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,8);
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usleep(TIME_DIV_FREESCALE*100*1000);
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jtag_add_reset(0,0);
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usleep(TIME_DIV_FREESCALE*300*1000);
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instr = JTAG_INSTR_ENABLE_ONCE;
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//Two rounds of jtag 0x6 (enable eonce) to enable EOnCE.
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for(int i = 0; i<3; i++){
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retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
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err_check_propagate(retval);
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}
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for(int i = 0; i<3; i++){
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instr_16 = 0x86;
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dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,16);
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instr_16 = 0xff;
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dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,16);
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}
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// Verify that debug mode is enabled
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uint16_t data_read_from_dr;
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retval = eonce_read_status_reg(target,&data_read_from_dr);
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err_check_propagate(retval);
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if((data_read_from_dr&0x30) == 0x30){
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LOG_DEBUG("EOnCE successfully entered debug mode.");
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target->state = TARGET_HALTED;
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retval = ERROR_OK;
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}else{
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LOG_DEBUG("Failed to set EOnCE module to debug mode.");
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retval = ERROR_TARGET_FAILURE;
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}
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if(eonce_status!=NULL)
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*eonce_status = data_read_from_dr;
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return retval;
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}
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/**
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* Puts the core into debug mode, enabling the EOnCE module.
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* This will not always work, eonce_enter_debug_mode executes much
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* more complicated routine, which is guaranteed to work, but requires
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* a reset. This will complicate comm with the flash module, since
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* after a reset clock divisors must be set again.
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* This implementation works most of the time, and is not accesible to the
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* user.
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*
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* @param target
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* @param eonce_status Data read from the EOnCE status register.
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*
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* @return
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*/
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static int eonce_enter_debug_mode_without_reset(struct target * target, uint16_t * eonce_status){
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int retval;
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uint32_t instr = JTAG_INSTR_DEBUG_REQUEST;
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uint32_t ir_out;//not used, just to make jtag happy.
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@ -475,10 +628,10 @@ static int eonce_enter_debug_mode(struct target * target, uint16_t * eonce_statu
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if((data_read_from_dr&0x30) == 0x30){
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LOG_DEBUG("EOnCE successfully entered debug mode.");
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target->state = TARGET_HALTED;
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return ERROR_OK;
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retval = ERROR_OK;
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}else{
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retval = ERROR_TARGET_FAILURE;
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err_check(retval,"Failed to set EOnCE module to debug mode.");
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err_check(retval,"Failed to set EOnCE module to debug mode. Try with halt");
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}
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if(eonce_status!=NULL)
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*eonce_status = data_read_from_dr;
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@ -551,7 +704,7 @@ static int dsp5680xx_halt(struct target *target){
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return ERROR_OK;
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}
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retval = eonce_enter_debug_mode(target,&eonce_status);
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err_check_propagate(retval);
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err_check(retval,"Failed to halt target.");
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retval = eonce_pc_store(target);
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err_check_propagate(retval);
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//TODO is it useful to store the pc?
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@ -1210,7 +1363,7 @@ static int dsp5680xx_f_signature(struct target * target, uint32_t address, uint3
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int retval;
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uint16_t hfm_ustat;
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if (dsp5680xx_target_status(target,NULL,NULL) != TARGET_HALTED){
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retval = eonce_enter_debug_mode(target,NULL);
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retval = eonce_enter_debug_mode_without_reset(target,NULL);
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err_check_propagate(retval);
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}
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retval = dsp5680xx_f_execute_command(target,HFM_CALCULATE_DATA_SIGNATURE,address,words,&hfm_ustat,1);
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@ -1341,7 +1494,7 @@ int dsp5680xx_f_erase(struct target * target, int first, int last){
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const uint16_t pgm_write_pflash[] = {0x8A46,0x0013,0x407D,0xE700,0xE700,0x8A44,0xFFFE,0x017B,0xE700,0xF514,0x8563,0x8646,0x0020,0x0014,0x8646,0x0080,0x0013,0x8A46,0x0013,0x2004,0x8246,0x0013,0x0020,0xA968,0x8A46,0x0013,0x1065,0x8246,0x0013,0x0010,0xA961};
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const uint32_t pgm_write_pflash_length = 31;
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int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count){
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int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count, int is_flash_lock){
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int retval = ERROR_OK;
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if (dsp5680xx_target_status(target,NULL,NULL) != TARGET_HALTED){
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retval = eonce_enter_debug_mode(target,NULL);
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@ -1351,10 +1504,12 @@ int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, ui
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// Download the pgm that flashes.
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// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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uint32_t my_favourite_ram_address = 0x8700; // This seems to be a safe address. This one is the one used by codewarrior in 56801x_flash.cfg
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if(!is_flash_lock){
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retval = dsp5680xx_write(target, my_favourite_ram_address, 1, pgm_write_pflash_length*2,(uint8_t *) pgm_write_pflash);
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err_check_propagate(retval);
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retval = dsp5680xx_execute_queue();
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err_check_propagate(retval);
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}
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// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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// Set hfmdiv
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// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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@ -1422,8 +1577,9 @@ int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, ui
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dsp5680xx_context.flush = 0;
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}
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dsp5680xx_context.flush = 1;
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if(!is_flash_lock){
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// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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// Verify flash
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// Verify flash (skip when exec lock sequence)
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// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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uint16_t signature;
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uint16_t pc_crc;
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@ -1434,31 +1590,138 @@ int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, ui
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retval = ERROR_FAIL;
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err_check(retval,"Flashed data failed CRC check, flash again!");
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}
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}
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return retval;
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}
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// Reset state machine
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int reset_jtag(void){
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int retval;
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tap_state_t states[2];
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const char *cp = "RESET";
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states[0] = tap_state_by_name(cp);
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retval = jtag_add_statemove(states[0]);
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err_check_propagate(retval);
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retval = jtag_execute_queue();
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err_check_propagate(retval);
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jtag_add_pathmove(0, states + 1);
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retval = jtag_execute_queue();
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return retval;
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}
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int dsp5680xx_f_unlock(struct target * target){
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int retval;
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if(target->tap->enabled){
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//TODO find a way to switch to the master tap here.
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LOG_ERROR("Master tap must be enabled to unlock flash.");
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return ERROR_TARGET_FAILURE;
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int retval = ERROR_OK;
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uint16_t eonce_status;
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uint32_t instr;
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uint32_t ir_out;
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uint16_t instr_16;
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uint16_t read_16;
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struct jtag_tap * tap_chp;
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struct jtag_tap * tap_cpu;
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tap_chp = jtag_tap_by_string("dsp568013.chp");
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if(tap_chp == NULL){
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retval = ERROR_FAIL;
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err_check(retval,"Failed to get master tap.");
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}
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uint32_t data_to_shift_in = MASTER_TAP_CMD_FLASH_ERASE;
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uint32_t data_shifted_out;
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retval = dsp5680xx_irscan(target,&data_to_shift_in,&data_shifted_out,8);
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tap_cpu = jtag_tap_by_string("dsp568013.cpu");
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if(tap_cpu == NULL){
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retval = ERROR_FAIL;
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err_check(retval,"Failed to get master tap.");
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}
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retval = eonce_enter_debug_mode(target,&eonce_status);
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if(retval == ERROR_OK){
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LOG_WARNING("Memory was not locked.");
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}
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jtag_add_reset(0,1);
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usleep(TIME_DIV_FREESCALE*200*1000);
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retval = reset_jtag();
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err_check(retval,"Failed to reset JTAG state machine");
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usleep(150);
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// Enable core tap
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tap_chp->enabled = true;
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retval = switch_tap(target,tap_chp,tap_cpu);
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err_check_propagate(retval);
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data_to_shift_in = HFM_CLK_DEFAULT;
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retval = dsp5680xx_drscan(target,((uint8_t *) & data_to_shift_in),((uint8_t *)&data_shifted_out),8);
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instr = JTAG_INSTR_DEBUG_REQUEST;
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retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
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err_check_propagate(retval);
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usleep(TIME_DIV_FREESCALE*100*1000);
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jtag_add_reset(0,0);
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usleep(TIME_DIV_FREESCALE*300*1000);
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// Enable master tap
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tap_chp->enabled = false;
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retval = switch_tap(target,tap_chp,tap_cpu);
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err_check_propagate(retval);
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// Execute mass erase to unlock
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instr = MASTER_TAP_CMD_FLASH_ERASE;
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retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_MASTER_TAP_IRLEN);
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err_check_propagate(retval);
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instr = HFM_CLK_DEFAULT;
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retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & ir_out,16);
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err_check_propagate(retval);
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usleep(TIME_DIV_FREESCALE*150*1000);
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jtag_add_reset(0,1);
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usleep(TIME_DIV_FREESCALE*200*1000);
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retval = reset_jtag();
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err_check(retval,"Failed to reset JTAG state machine");
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usleep(150);
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instr = 0x0606ffff;
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retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & ir_out,32);
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err_check_propagate(retval);
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// enable core tap
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instr = 0x5;
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retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_MASTER_TAP_IRLEN);
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err_check_propagate(retval);
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instr = 0x2;
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retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & ir_out,4);
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err_check_propagate(retval);
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tap_cpu->enabled = true;
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tap_chp->enabled = false;
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instr = JTAG_INSTR_ENABLE_ONCE;
|
||||
//Two rounds of jtag 0x6 (enable eonce) to enable EOnCE.
|
||||
retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
|
||||
err_check_propagate(retval);
|
||||
instr = JTAG_INSTR_DEBUG_REQUEST;
|
||||
retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
|
||||
err_check_propagate(retval);
|
||||
instr_16 = 0x1;
|
||||
retval = dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,8);
|
||||
instr_16 = 0x20;
|
||||
retval = dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,8);
|
||||
usleep(TIME_DIV_FREESCALE*100*1000);
|
||||
jtag_add_reset(0,0);
|
||||
usleep(TIME_DIV_FREESCALE*300*1000);
|
||||
return retval;
|
||||
}
|
||||
|
||||
int dsp5680xx_f_lock(struct target * target){
|
||||
int retval;
|
||||
uint16_t lock_word[] = {HFM_LOCK_FLASH,HFM_LOCK_FLASH};
|
||||
retval = dsp5680xx_f_wr(target,(uint8_t *)(lock_word),HFM_LOCK_ADDR_L,4);
|
||||
uint16_t lock_word[] = {HFM_LOCK_FLASH};
|
||||
retval = dsp5680xx_f_wr(target,(uint8_t *)(lock_word),HFM_LOCK_ADDR_L,2,1);
|
||||
err_check_propagate(retval);
|
||||
|
||||
jtag_add_reset(0,1);
|
||||
usleep(TIME_DIV_FREESCALE*200*1000);
|
||||
|
||||
retval = reset_jtag();
|
||||
err_check(retval,"Failed to reset JTAG state machine");
|
||||
usleep(TIME_DIV_FREESCALE*100*1000);
|
||||
jtag_add_reset(0,0);
|
||||
usleep(TIME_DIV_FREESCALE*300*1000);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -69,10 +69,10 @@
|
|||
//----------------------------------------------------------------
|
||||
// Master TAP instructions from MC56F8000RM.pdf
|
||||
//----------------------------------------------------------------
|
||||
#define MASTER_TAP_CMD_BYPASS 0xFF
|
||||
#define MASTER_TAP_CMD_IDCODE 0x02
|
||||
#define MASTER_TAP_CMD_TLM_SEL 0x05
|
||||
#define MASTER_TAP_CMD_FLASH_ERASE 0x08
|
||||
#define MASTER_TAP_CMD_BYPASS 0xF
|
||||
#define MASTER_TAP_CMD_IDCODE 0x2
|
||||
#define MASTER_TAP_CMD_TLM_SEL 0x5
|
||||
#define MASTER_TAP_CMD_FLASH_ERASE 0x8
|
||||
//----------------------------------------------------------------
|
||||
|
||||
//----------------------------------------------------------------
|
||||
|
|
@ -234,10 +234,11 @@ static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target *target
|
|||
* @param buffer
|
||||
* @param address Word addressing.
|
||||
* @param count In bytes.
|
||||
* @param verify_flash Execute a CRC check after flashing.
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count);
|
||||
int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count, int is_flash_lock);
|
||||
|
||||
/**
|
||||
* The FM has the funcionality of checking if the flash array is erased. This function executes it. It does not support individual sector analysis.
|
||||
|
|
|
|||
|
|
@ -36,7 +36,11 @@ set _TARGETNAME $_CHIPNAME.cpu
|
|||
target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# Setup the interesting tap
|
||||
jtag configure $_CHIPNAME.chp -event setup "jtag tapenable $_TARGETNAME"
|
||||
# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations requiere certain instruction to be in the IR register during reset, and polling would change this)
|
||||
jtag configure $_CHIPNAME.chp -event setup "
|
||||
jtag tapenable $_TARGETNAME
|
||||
poll off
|
||||
"
|
||||
|
||||
#select CORE tap by modifying the TLM register.
|
||||
#to be used when MASTER tap is selected.
|
||||
|
|
|
|||
Loading…
Reference in New Issue