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Support for KaRo TX25 CPU Module on a StarterkitV base board 

This patch adds support for the KaRo TX25 module on a StarterkitV base board.
For board details, check http://www.karo-electronics.com/tx25.html

Change-Id: I2c80c5467bc476955b55196728aa3c37c8185e6c
Author: Simon Widmer <simonxwidmer@gmail.com>
Signed-off-by: Mark Vels <mark.vels@team-embedded.nl>
Reviewed-on: http://openocd.zylin.com/557
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Simon Widmer 2012-04-04 16:34:29 +02:00 committed by Spencer Oliver
parent 7743e0fb43
commit fad7240689
1 changed files with 158 additions and 0 deletions
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158
tcl/board/tx25_stk5.cfg Normal file
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# -------------------------------------------------------------------------
# KaRo TX25 CPU Module on a StarterkitV base board
# http://www.karo-electronics.com/tx25.html
# -------------------------------------------------------------------------
source [find tcl/target/imx25.cfg]
#-------------------------------------------------------------------------
# Declare Nand
#-------------------------------------------------------------------------
nand device K9F1G08UOC mxc imx25.cpu mx25 hwecc biswap
$_TARGETNAME configure -event gdb-attach { reset init }
$_TARGETNAME configure -event reset-init { tx25_init }
proc tx25_init { } {
#-------------------------------------------------------------------------
# AIPS setup - Only setup MPROTx registers. The PACR default values are good.
# Set all MPROTx to be non-bufferable, trusted for R/W,
# not forced to user-mode.
#-------------------------------------------------------------------------
mww 0x43f00000 0x77777777
mww 0x43f00004 0x77777777
mww 0x53f00000 0x77777777
mww 0x53f00004 0x77777777
sleep 100
#-------------------------------------------------------------------------
# MAX (Multi-Layer AHB Crossbar Switch) setup
# MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
#-------------------------------------------------------------------------
mww 0x43f04000 0x00043210
mww 0x43f04100 0x00043210
mww 0x43f04200 0x00043210
mww 0x43f04300 0x00043210
mww 0x43f04400 0x00043210
# SGPCR - always park on last master
mww 0x43f04010 0x10
mww 0x43f04110 0x10
mww 0x43f04210 0x10
mww 0x43f04310 0x10
mww 0x43f04410 0x10
# MGPCR - restore default values
mww 0x43f04800 0x0
mww 0x43f04900 0x0
mww 0x43f04a00 0x0
mww 0x43f04b00 0x0
mww 0x43f04c00 0x0
# Configure M3IF registers
# M3IF Control Register (M3IFCTL) for MX25
# MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
# MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
# MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
# MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000
# MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
# MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000
# MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000
# MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
# ----------
# 0x00000001
mww 0xb8003000 0x00000001
#-------------------------------------------------------------------------
# configure ARM CLK
#-------------------------------------------------------------------------
# Set the Clock CTL (HRM p. 355)
mww 0x53F80008 0x20034000
# Setup Clock Gating CTL 0-2 (HRM p. 357)
mww 0x53F8000C 0x1fffffff
mww 0x53F80010 0xffffffff
mww 0x53F80014 0x000fdfff
#-------------------------------------------------------------------------
# SDRAM initialization
#-------------------------------------------------------------------------
# set to 3.3v SDRAM
mww 0x43FAC454 0x00000800
# reset (set up ESDMISC)
mww 0xB8001010 0x00000002
# Setup for SDRAM Bank 0
#-------------------------------------------------------------------------
# Write ESDCFG0
mww 0xB8001004 0x00095728
# CTL SMode = Precharge command
mww 0xB8001000 0x92116480
mww 0x80000400 0x00000000
# CTL SMode = Auto Refresh command
mww 0xB8001000 0xA2116480
mww 0x80000000 0x0
mww 0x80000000 0x0
mww 0x80000000 0x0
mww 0x80000000 0x0
mww 0x80000000 0x0
mww 0x80000000 0x0
mww 0x80000000 0x0
mww 0x80000000 0x0
# CTL SMode = Load Mode Register command
mww 0xB8001000 0xB2116480
mwb 0x80000033 0x00
# CTL SMode = normal
mww 0xB8001000 0x82116480
# Setup for SDRAM Bank 1
#-------------------------------------------------------------------------
# Write ESDCFG1
mww 0xB800100C 0x00095728
# CTL SMode = Precharge command
mww 0xB8001008 0x92116480
mww 0x90000400 0x00000000
# CTL SMode = Auto Refresh command
mww 0xB8001008 0xA2116480
mww 0x90000000 0x00000000
mww 0x90000000 0x00000000
mww 0x90000000 0x00000000
mww 0x90000000 0x00000000
mww 0x90000000 0x00000000
mww 0x90000000 0x00000000
mww 0x90000000 0x00000000
mww 0x90000000 0x00000000
# CTL SMode = Load Mode Register command
mww 0xB8001008 0xB2116480
mwb 0x90000033 0x00
# CTL SMode = normal
mww 0xB8001008 0x82116480
# GPIO configuration
#-------------------------------------------------------------------------
mww 0x43FAC02C 0x00000015
mww 0x53FD0000 0x01000000
mww 0x53FD0004 0x00000080
}