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101
.gitignore vendored
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# stuff "git status" should ignore
# build output
.libs
.deps
.dirstamp
*.o
*.o.??????
*.a
*.lo
*.la
*.in
# generated source files
src/jtag/minidriver_imp.h
src/jtag/jtag_minidriver.h
# OpenULINK driver files generated by SDCC
src/jtag/drivers/OpenULINK/*.rel
src/jtag/drivers/OpenULINK/*.asm
src/jtag/drivers/OpenULINK/*.lst
src/jtag/drivers/OpenULINK/*.sym
src/jtag/drivers/OpenULINK/*.map
src/jtag/drivers/OpenULINK/*.mem
src/jtag/drivers/OpenULINK/*.lk
src/jtag/drivers/OpenULINK/*.ihx
src/jtag/drivers/OpenULINK/*.rst
# editor files
*.swp
src/startup.tcl
startup_tcl.inc
xscale_debug.inc
bin2char
bin2char.exe
doc/openocd.aux
doc/openocd.cp
doc/openocd.cps
doc/openocd.fn
doc/openocd.fns
doc/openocd.html
doc/openocd.info
doc/openocd.info-1
doc/openocd.info-2
doc/openocd.ky
doc/openocd.log
doc/openocd.pdf
doc/openocd.pg
doc/openocd.toc
doc/openocd.tp
doc/openocd.vr
doc/texinfo.tex
doc/version.texi
src/openocd
src/openocd.exe
# configure/autotools output
aclocal.m4
autom4te.cache
compile
config.*
configure
depcomp
doxygen
doxygen.log
Doxyfile
install-sh
libtool
ltmain.sh
Makefile
!contrib/loaders/**/Makefile
mdate-sh
missing
stamp-h1
stamp-vti
INSTALL
NOTES
# coexist with quilt
patches
*.patch
# Eclipse stuff
.project
.cproject
.settings
# Emacs temp files
*~
# Emacs TAGS file
TAGS
# CScope database files
*cscope.out
# ctags tag files
tags

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.gitmodules vendored
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[submodule "tools/git2cl"]
path = tools/git2cl
url = http://repo.or.cz/r/git2cl.git
[submodule "jimtcl"]
path = jimtcl
url = http://repo.or.cz/r/jimtcl.git
[submodule "src/jtag/drivers/libjaylink"]
path = src/jtag/drivers/libjaylink
url = http://repo.or.cz/r/libjaylink.git

12
AUTHORS
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Dominic Rath <Dominic.Rath@gmx.de>
Magnus Lundin <lundin@mlu.mine.nu>
Michael Fischer <fischermi@t-online.de>
Spencer Oliver <spen@spen-soft.co.uk>
Carsten Schlote <schlote@vahanus.net>
Øyvind Harboe <oyvind.harboe@zylin.com>
Duane Ellis <openocd@duaneellis.com>
Michael Schwingen <michael@schwingen.org>
Rick Altherr <kc8apf@users.berlios.de>
David Brownell <dbrownell@users.sourceforge.net>
Vincint Palatin <vpalatin@users.berlios.de>
Zachary T Welch <zw@superlucidity.net>

10
AUTHORS.ChangeLog
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drath:Dominic Rath <Dominic.Rath@gmx.de>
mlu:Magnus Lundin <lundin@mlu.mine.nu>
mifi:Michael Fischer <fischermi@t-online.de>
ntfreak:Spencer Oliver <spen@spen-soft.co.uk>
duane:Duane Ellis <openocd@duaneellis.com>
oharboe:Øyvind Harboe <oyvind.harboe@zylin.com>
kc8apf:Rick Altherr <kc8apf@users.berlios.de>
zwelch:Zachary T Welch <zw@superlucidity.net>
vpalatin:Vincent Palatin <vpalatin@users.berlios.de>
bodylove:Carsten Schlote <schlote@vahanus.net>

74
BUGS
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// This file is part of the Doxygen Developer Manual
/** @page bugs Bug Reporting
Please report bugs by subscribing to the OpenOCD mailing list and
posting a message with your report:
openocd-devel@lists.sourceforge.net
Also, please check the bug database to see if a ticket for
the bug has already been opened. You might be asked to open
such a ticket, or to update an existing ticket with more data.
http://bugs.openocd.org/
To minimize work for OpenOCD developers, you should try to include
all of the information listed below. If you feel that some of the
items below are unnecessary for a clear bug report, you may leave
them out; likewise, feel free to include additional information
that may be important.
- Target PCB/board description
- Configuration scripts
- OpenOCD command line
- List of commands issued or GDB operations performed
- Expected result
- Actual result
- Logs using <code>debug_level 3</code> (or with '-d 3' on the command line)
- If the report is for a regression:
- Include logs for both working and broken versions.
- Find the precise version that caused the regression by binary search.
You can use "git bisect" to expedite this binary search:
http://www.kernel.org/pub/software/scm/git/docs/git-bisect.html
If possible, please develop and attach a patch that helps to expose or
solve the reported problem. See the HACKING file for information
about that process.
Attach all files directly to your posting. The mailing list knows to
transform attachments to links, but attachments must be less than 300KB
in total.
@section bugscrashdump Obtaining Crash Backtraces
If OpenOCD is crashing, there are two very effective things you can do to
improve your chances of getting help on the development mailing list.
Try to reproduce the problem using the dummy JTAG interface to allow other developers to replicate
your problem robustly and use GDB to get a trace:@par
@code
% OPENOCDSRC/configure --enable-dummy ...
% openocd -f interface/dummy.cfg -f target/xxx.cfg
=> SEGFAULT
% gdb --args openocd ....
(gdb) run
(gdb) bt
=> here a stack trace is dumped.
@endcode
@section bugsintreedebug Running and Debugging In-Tree
To run or debug the in-tree executable (not recommended), you must
use libtool to set up the correct shared library paths:
@code
libtool gdb --args openocd ....
@endcode
or the more pedantic (and forward-compatible):
@code
libtool --mode=execute gdb --args openocd ....
@endcode
*/
/** @file
This file contains the @ref bugs page.
*/

339
COPYING
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@ -1,339 +0,0 @@
GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The licenses for most software are designed to take away your
freedom to share and change it. By contrast, the GNU General Public
License is intended to guarantee your freedom to share and change free
software--to make sure the software is free for all its users. This
General Public License applies to most of the Free Software
Foundation's software and to any other program whose authors commit to
using it. (Some other Free Software Foundation software is covered by
the GNU Lesser General Public License instead.) You can apply it to
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When we speak of free software, we are referring to freedom, not
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We protect your rights with two steps: (1) copyright the software, and
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TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains
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END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
convey the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) <year> <name of author>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) year name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may
be called something other than `show w' and `show c'; they could even be
mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
<signature of Ty Coon>, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License.

1
ChangeLog
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Retired in favor of git log.

1517
Doxyfile.in
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185
HACKING
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// This file is part of the Doxygen Developer Manual
/** @page patchguide Patch Guidelines
\attention If you're behind a corporate wall with http only access to the
world, you can still use these instructions!
\attention You can't send patches to the mailing list anymore at all. Nowadays
you are expected to send patches to the OpenOCD Gerrit GIT server for a
review.
@section gerrit Submitting patches to the OpenOCD Gerrit server
OpenOCD is to some extent a "self service" open source project, so to
contribute, you must follow the standard procedures to have the best
possible chance to get your changes accepted.
The procedure to create a patch is essentially:
- make the changes
- create a commit
- send the changes to the Gerrit server for review
- correct the patch and re-send it according to review feedback
Your patch (or commit) should be a "good patch": focus it on a single
issue, and make it be easily reviewable. Don't make
it so large that it's hard to review; split large
patches into smaller ones. (That can also help
track down bugs later on.) All patches should
be "clean", which includes preserving the existing
coding style and updating documentation as needed.
Say in the commit message if it's a bugfix (describe the bug) or a new
feature. Don't expect patches to merge immediately
for the next release. Be ready to rework patches
in response to feedback.
Add yourself to the GPL copyright for non-trivial changes.
@section stepbystep Step by step procedure
-# Create a Gerrit account at: http://openocd.zylin.com
- On subsequent sign ins, use the full URL prefaced with 'http://'
For example: http://user_identifier.open_id_provider.com
-# Add a username to your profile.
After creating the Gerrit account and signing in, you will need to
add a username to your profile. To do this, go to 'Settings', and
add a username of your choice.
Your username will be required in step 3 and substituted wherever
the string 'USERNAME' is found.
-# Create an SSH public key following the directions on github:
https://help.github.com/articles/generating-ssh-keys . You can skip step 3
(adding key to Github account) and 4 (testing) - these are useful only if
you actually use Github or want to test whether the new key works fine.
-# Add this new SSH key to your Gerrit account:
go to 'Settings' > 'SSH Public Keys', paste the contents of
~/.ssh/id_rsa.pub into the text field (if it's not visible click on
'Add Key ...' button) and confirm by clicking 'Add' button.
-# Clone the git repository, rather than just download the source:
@code
git clone git://git.code.sf.net/p/openocd/code openocd
@endcode
or if you have problems with the "git:" protocol, use
the slower http protocol:
@code
git clone http://git.code.sf.net/p/openocd/code openocd
@endcode
-# Set up Gerrit with your local repository. All this does it
to instruct git locally how to send off the changes.
-# Add a new remote to git using Gerrit username:
@code
git remote add review ssh://USERNAME@openocd.zylin.com:29418/openocd.git
git config remote.review.push HEAD:refs/publish/master
@endcode
Or with http only:
@code
git remote add review http://USERNAME@openocd.zylin.com/p/openocd.git
git config remote.review.push HEAD:refs/publish/master
@endcode
The http password is configured from your gerrit settings - http://openocd.zylin.com/#/settings/http-password.
\note If you want to simplify http access you can also add your http password to the url as follows:
@code
git remote add review http://USERNAME:PASSWORD@openocd.zylin.com/p/openocd.git
@endcode
-# You will need to install this hook, we will look into a better solution:
@code
scp -p -P 29418 USERNAME@openocd.zylin.com:hooks/commit-msg .git/hooks/
@endcode
Or with http only:
@code
wget http://openocd.zylin.com/tools/hooks/commit-msg
mv commit-msg .git/hooks
chmod +x .git/hooks/commit-msg
@endcode
\note A script exists to simplify the two items above. execute:
@code
tools/initial.sh <username>
@endcode
With @<username@> being your Gerrit username.
-# Set up git with your name and email:
@code
git config --global user.name "John Smith"
git config --global user.email "john@smith.org"
@endcode
-# Work on your patches. Split the work into
multiple small patches that can be reviewed and
applied seperately and safely to the OpenOCD
repository.
@code
while(!done) {
work - edit files using your favorite editor.
run "git commit -s -a" to commit all changes.
run tools/checkpatch.sh to verify your patch style is ok.
}
@endcode
\note use "git add ." before commit to add new files.
Comment template, notice the short first line w/topic. The topic field
should identify the main part or subsystem the patch touches. Check
git log for examples.
@code
topic: Short comment
<blank line>
Longer comments over several lines, explaining (where applicable) the
reason for the patch and the general idea the solution is based on,
any major design decisions, etc...
<blank line>
Signed-off-by: ...
@endcode
-# Next you need to make sure that your patches
are on top of the latest stuff on the server and
that there are no conflicts:
@code
git pull --rebase origin master
@endcode
-# Send the patches to the Gerrit server for review:
@code
git push review
@endcode
-# Forgot something, want to add more? Just make the changes and do:
@code
git commit --amend
git push review
@endcode
Further reading: http://www.coreboot.org/Git
@section timeline When can I expect my contribution to be committed?
The code review is intended to take as long as a week or two to allow
maintainers and contributors who work on OpenOCD only in their spare
time oportunity to perform a review and raise objections.
With Gerrit much of the urgency of getting things committed has been
removed as the work in progress is safely stored in Gerrit and
available if someone needs to build on your work before it is
submitted to the official repository.
Another factor that contributes to the desire for longer cool-off
times (the time a patch lies around without any further changes or
comments), it means that the chances of quality regression on the
master branch will be much reduced.
If a contributor pushes a patch, it is considered good form if another
contributor actually approves and submits that patch.
It should be noted that a negative review in Gerrit ("-1" or "-2") may (but does
not have to) be disregarded if all conditions listed below are met:
- the concerns raised in the review have been addressed (or explained),
- reviewer does not re-examine the change in a month,
- reviewer does not answer e-mails for another month.
@section browsing Browsing Patches
All OpenOCD patches can be reviewed <a href="http://openocd.zylin.com/">here</a>.
@section reviewing Reviewing Patches
From the main <a href="http://openocd.zylin.com/#/q/status:open,n,z">Review
page</a> select the patch you want to review and click on that patch. On the
appearing page select the download method (top right). Apply the
patch. After building and testing you can leave a note with the "Reply"
button and mark the patch with -1, 0 and +1.
*/
/** @file
This file contains the @ref patchguide page.
*/

112
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@ -1,112 +0,0 @@
# not a GNU package. You can remove this line, if
# have all needed files, that a GNU package needs
AUTOMAKE_OPTIONS = gnu 1.6
# make sure we pass the correct jimtcl flags to distcheck
DISTCHECK_CONFIGURE_FLAGS = --disable-install-jim
nobase_dist_pkgdata_DATA = \
contrib/libdcc/dcc_stdio.c \
contrib/libdcc/dcc_stdio.h \
contrib/libdcc/example.c \
contrib/libdcc/README \
contrib/99-openocd.rules
if INTERNAL_JIMTCL
SUBDIRS = jimtcl
else
SUBDIRS =
endif
SUBDIRS += src doc
EXTRA_DIST = \
BUGS \
HACKING \
NEWTAPS \
README.Windows \
README.OSX \
$(wildcard $(srcdir)/NEWS*) \
Doxyfile.in \
tools/logger.pl \
tools/rlink_make_speed_table \
tools/st7_dtc_as \
contrib
libtool: $(LIBTOOL_DEPS)
$(SHELL) ./config.status --recheck
docs: pdf html doxygen
Doxyfile: $(srcdir)/Doxyfile.in
@echo "Creating $@ from $<..."
@( \
echo "### @@@ -= DO NOT EDIT THIS FILE =- @@@ ###" && \
echo "### @@@ Make changes to Doxyfile.in @@@ ###" && \
sed -e 's,@srcdir\@,$(srcdir),' \
-e 's,@builddir\@,$(builddir),' \
-e 's,@doxygen_as_html\@,$(doxygen_as_html),' \
-e 's,@doxygen_as_pdf\@,$(doxygen_as_pdf),' $< \
) > $@
THE_MANUAL = doxygen/latex/refman.pdf
doxygen::
$(MAKE) Doxyfile
doxygen Doxyfile 2>&1 | perl $(srcdir)/tools/logger.pl > doxygen.log
@if [ -f doxygen/latex/refman.tex ]; then \
echo "Creating $(THE_MANUAL)..."; \
$(MAKE) $(THE_MANUAL); \
else \
echo "Skipping Doxygen PDF..."; \
fi
$(THE_MANUAL): %.pdf: %.tex
-cd $$(dirname $*) && pdflatex $$(basename $*)
-cd $$(dirname $*) && pdflatex $$(basename $*)
TCL_PATH = tcl
# command to find paths of script files, relative to TCL_PATH
TCL_FILES = find $(srcdir)/$(TCL_PATH) -name '*.cfg' -o -name '*.tcl' -o -name '*.txt' | \
sed -e 's,^$(srcdir)/$(TCL_PATH),,'
dist-hook:
if test -d $(srcdir)/.git -a \( ! -e $(distdir)/ChangeLog -o -w $(distdir)/ChangeLog \) ; then \
git --git-dir $(srcdir)/.git log | $(srcdir)/tools/git2cl/git2cl > $(distdir)/ChangeLog ; \
fi
for i in $$($(TCL_FILES)); do \
j="$(distdir)/$(TCL_PATH)/$$i" && \
mkdir -p "$$(dirname $$j)" && \
$(INSTALL_DATA) $(srcdir)/$(TCL_PATH)/$$i $$j; \
done
install-data-hook:
for i in $$($(TCL_FILES)); do \
j="$(DESTDIR)$(pkgdatadir)/scripts/$$i" && \
mkdir -p "$$(dirname $$j)" && \
$(INSTALL_DATA) $(srcdir)/$(TCL_PATH)/$$i $$j; \
done
uninstall-hook:
rm -rf $(DESTDIR)$(pkgdatadir)/scripts
distclean-local:
rm -rf Doxyfile doxygen
rm -f $(srcdir)/jimtcl/configure.gnu
DISTCLEANFILES = doxygen.log
MAINTAINERCLEANFILES = \
$(srcdir)/INSTALL \
$(srcdir)/configure \
$(srcdir)/Makefile.in \
$(srcdir)/depcomp \
$(srcdir)/config.guess \
$(srcdir)/config.sub \
$(srcdir)/config.h.in \
$(srcdir)/config.h.in~ \
$(srcdir)/compile \
$(srcdir)/ltmain.sh \
$(srcdir)/missing \
$(srcdir)/aclocal.m4 \
$(srcdir)/install-sh

33
NEWS
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This file includes highlights of the changes made in the OpenOCD
source archive release.
JTAG Layer:
Boundary Scan:
Target Layer:
Flash Layer:
Board, Target, and Interface Configuration Scripts:
Server Layer:
Documentation:
Build and Release:
This release also contains a number of other important functional and
cosmetic bugfixes. For more details about what has changed since the
last release, see the git repository history:
http://sourceforge.net/p/openocd/code/ci/v0.x.0/log/?path=
For older NEWS, see the NEWS files associated with each release
(i.e. NEWS-<version>).
For more information about contributing test reports, bug fixes, or new
features and device support, please read the new Developer Manual (or
the BUGS and PATCHES.txt files in the source archive).

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NEWS-0.2.0
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The OpenOCD 0.2.0 source archive release includes numerous improvements
that were made since the initial 0.1.0 source archive release. Many
contributors helped make this release a great success, and the community
of developers and maintainers look forward to any response.
In addition to the list of changes below, countless bug fixing and
cleaning was performed across the tree. Various TCL command parameters
must past stricter value checks, and many more error conditions have
been handled correctly. These efforts helped to make the 0.2.0 release
more stable and robust, though some changes may expose latent bugs in
your existing configuration scripts.
This release does not maintain backward compatibility in all respects,
so some target or configuration scripts may need to be updated. In some
cases, you may also see warnings; resolve those, because they indicate
commands that will be removed in the future.
The following areas of OpenOCD functionality changed in this release:
JTAG Layer:
- Improves modularity: core, TCL, driver commands, and interface have
been separated, encapsulated, and documented for developers. Mostly.
- Improves JTAG TAP transition tables:
* Makes TAP paths variable length, rather than being fixed at 7 steps.
* Fixes problems with some targets that did not like longer paths.
- Improves JTAG driver/minidriver modularity and encapsulation.
- New drivers:
* Adds stub minidriver for developing new embedded JTAG interfaces.
- Improves drivers:
* ft2232+ftd2xx:
+ Adds initial high-speed device support: --enable-ftd2xx-highspeed
+ Supports more types of FTDI-based devices.
* jlink:
+ Works with more versions of the firmware (v3 and newer)
+ Supports dynamically detects device capabilities and limits
* vsllink:
+ Supports very long scan chains
* amtjtagaccel:
+ Fixes broken ID code detection problems.
Target Layer:
- New devices: AVR, FA526
- Improved support: ARM ADI, ARM11, MIPS
- Numerous other bug fixes and improvements
Flash Layer:
- Improved drivers: mflash
- New drivers: AT91SAM3, AVR, Davinci NAND
Board, Interface, and Target Configuration Scripts:
- Many new and improved targets and boards are now available.
- Better separation of "board" and "target" configuration
- Moved all TCL files to top-level "tcl" directory in the source tree
- Installation moved from '$pkglibdir/' to '$pkgdatadir/scripts/'.
- Site-specific files should be installed under '$pkgdatadir/site/';
files that exist this tree will be used in preference to default
distribution configurations in '$pkgdatadir/scripts/'.
Documentation:
- Updated User Guide: http://openocd.berlios.de/doc/html/index.html
* Partially re-written and re-organized.
* Standardized presentation for all commands.
* Covers many drivers and commands that were previously omitted.
* New index for commands and drivers.
- Added Developer Manual: http://openocd.berlios.de/doc/doxygen/index.html
* Now includes architecture, technical primers, style guides, and more.
* Available in-tree and on-line.
Build and Release:
- Increased configuration and compilation warning coverage.
* Use --disable-werror to work around build errors caused by warnings.
- Use libtool to produce helper libraries as a step toward "libopenocd".
- New processes and scripting to facilitate future source releases.
For more details about what has changed since 0.1.0, see the ChangeLog
associated with this release.
For more information about contributing test reports, bug fixes, or new
features and device support, please read the new Developer Manual (or
the BUGS and PATCHES files in the source archive).

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NEWS-0.3.0
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This file should include highlights of the changes made in the
OpenOCD openocd-0.3.0 source archive release. See the repository
history for details about what changed, including bugfixes and
other issues not mentioned here.
JTAG Layer:
FT2232H (high speed USB) support doesn't need separate configuration
New FT2232H JTAG adapters: Amontec, Olimex, Signalyzer
New reset_config options for SRST gating the JTAG clock (or not)
TAP declaration no longer requires ircapture and mask attributes
Scan chain setup should be more robust, with better diagnostics
New TAP events:
"post-reset" for TAP-invariant setup code (TAPs not usable yet)
"setup" for use once TAPs are addressable (e.g. with ICEpick)
Overridable Tcl "init_reset" and "jtag_init" procedures
Simple "autoprobe" mechanism to help simplify server setup
Boundary Scan:
SVF bugfixes ... parsing fixes, better STATE switch conformance
XSVF bugfixes ... be more correct, handle Xilinx tool output
Target Layer:
Warn on use of obsolete numeric target IDs
New commands for use with Cortex-M3 processors:
"cortex_m3 disassemble" ... Thumb2 disassembly (UAL format)
"cortex_m3 vector_catch" ... traps certain hardware faults
without tying up breakpoint resources
If you're willing to help debug it
VERY EARLY Cortex-A8 and ARMv7A support
Updated BeagleBoard.org hardware support
you may need to explicitly "reset" after connect-to-Beagle
New commands for use with XScale processors: "xscale vector_table"
ARM
bugfixes to single-stepping Thumb code
ETM: unavailable registers are not listed
ETB, ETM: report actual hardware status
ARM9
name change: "arm9 vector_catch" not "arm9tdmi vector_catch"
ARM11
single stepping support for i.MX31
bugfix for missing "arm11" prefix on "arm11 memwrite ..."
GDB support
gdb_attach command is gone
Flash Layer:
The lpc2000 driver handles the new NXP LPC1700 (Cortex-M3) chips
New drivers:
lpc2900, for NXP LPC2900 chips (ARM968 based)
mx3_nand, for imx31
New "last" flag for NOR "flash erase_sector" and "flash protect"
The "nand erase N" command now erases all of bank N
Speed up davinci_nand by about 3x
Board, Target, and Interface Configuration Scripts:
Amontec JTAGkey2 support
Cleanup and additions for the TI/Luminary Stellaris scripts
LPC1768 target (and flash) support
Keil MCB1700 eval board
Samsung s3c2450
Mini2440 board
Numeric TAP and Target identifiers now trigger warnings
PXA255 partially enumerates
Documentation:
Capture more debugging and setup advice
Notes on target source code changes that may help debugging
Build and Release:
Repository moved from SVN at Berlios to GIT at SourceForge
Clean builds on (32-bit) Cygwin
Clean builds on 64-bit MinGW
For more details about what has changed since the last release,
see the git repository history. With gitweb, you can browse that
in various levels of detail.
For older NEWS, see the NEWS files associated with each release
(i.e. NEWS-<version>).
For more information about contributing test reports, bug fixes, or new
features and device support, please read the new Developer Manual (or
the BUGS and PATCHES files in the source archive).

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NEWS-0.4.0
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This file includes highlights of the changes made in the
OpenOCD 0.4.0 source archive release. See the repository
history for details about what changed, including bugfixes
and other issues not mentioned here.
JTAG Layer:
Support KT-Link JTAG adapter.
Support USB-JTAG, Altera USB-Blaster and compatibles.
Boundary Scan:
Target Layer:
General
- Removed commands which have been obsolete for at least
a year (from both documentation and, sometimes, code).
- new "reset-assert" event, for systems without SRST
ARM
- supports "reset-assert" event (except on Cortex-M3)
- renamed "armv4_5" command prefix as "arm"
- recognize TrustZone "Secure Monitor" mode
- "arm regs" command output changed
- register names use "sp" not "r13"
- add top-level "mcr" and "mrc" commands, replacing
various core-specific operations
- basic semihosting support (ARM7/ARM9 only, for now)
ARM11
- Should act much more like other ARM cores:
* Preliminary ETM and ETB hookup
* accelerated "flash erase_check"
* accelerated GDB memory checksum
* support "arm regs" command
* can access all core modes and registers
* watchpoint support
- Shares some core debug code with Cortex-A8
Cortex-A8
- Should act much more like other ARM cores:
* support "arm regs" command
* can access all core modes and registers
* watchpoint support
- Shares some core debug code with ARM11
Cortex-M3
- Exposed DWT registers like cycle counter
- vector_catch settings not clobbered by resets
- no longer interferes with firmware's fault handling
ETM, ETB
- "trigger_percent" command moved ETM --> ETB
- "etm trigger_debug" command added
MIPS
- use fastdata writes
Freescale DSP563xx cores (partial support)
Flash Layer:
'flash bank' and 'nand device' take <bank_name> as first argument.
With this, flash/NAND commands allow referencing banks by name:
- <bank_name>: reference the bank with its defined name
- <driver_name>[.N]: reference the driver's Nth bank
New 'nand verify' command to check bank against an image file.
The "flash erase_address" command now rejects partial sectors;
previously it would silently erase extra data. If you
want to erase the rest of the first and/or last sectors
instead of failing, you must pass an explicit "pad" flag.
New at91sam9 NAND controller driver.
New s3c64xx NAND controller driver.
Board, Target, and Interface Configuration Scripts:
ARM9
- ETM and ETB hookup for iMX2* targets
Add $HOME/.openocd to the search path.
Handle Rev C of LM3S811 eval boards.
- use "luminary-lm3s811.cfg" for older boards
- use "luminary.cfg" for RevC and newer
Core Jim/TCL Scripting:
New 'usage' command to provide terse command help.
Improved command 'help' command output (sorted and indented).
Improved command handling:
- Most boolean settings now accept any of the following:
on/off, enable/disable, true/false, yes/no, 1/0
- More error checking and reporting.
Documentation:
New built-in command development documentation and primer.
Build and Release:
Use --enable-doxygen-pdf to build PDF developer documentation.
Consider upgrading to libftdi 0.17 if you use that library; it
includes bugfixes which improve FT2232H support.
For more details about what has changed since the last release,
see the git repository history. With gitweb, you can browse that
in various levels of detail.
For older NEWS, see the NEWS files associated with each release
(i.e. NEWS-<version>).
For more information about contributing test reports, bug fixes, or new
features and device support, please read the new Developer Manual (or
the BUGS and PATCHES.txt files in the source archive).

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NEWS-0.5.0
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This file includes highlights of the changes made in the
OpenOCD 0.5.0 source archive release. See the repository
history for details about what changed, including bugfixes
and other issues not mentioned here.
JTAG Layer:
New driver for "Bus Pirate"
Rename various commands so they're not JTAG-specific
There are migration procedures for most of these, but you should
convert your scripts to the new names, since those procedures
will not be around forever.
jtag jinterface ... is now adapter_name
jtag_khz ... is now adapter_khz
jtag_nsrst_delay ... is now adapter_nsrst_delay
jtag_nsrst_assert_width ... is now adapter_nsrst_assert_width
Support Voipac VPACLink JTAG Adapter.
Boundary Scan:
Transport framework core ... supporting future work for SWD, SPI, and other
non-JTAG ways to debug targets or program flash.
Target Layer:
ARM:
- basic semihosting support for ARMv7M.
- renamed "armv7m" command prefix as "arm"
MIPS:
- "ejtag_srst" variant removed. The same functionality is
obtained by using "reset_config none".
- added PIC32MX software reset support, this means srst is not
required to be connected anymore.
OTHER:
- preliminary AVR32 AP7000 support.
Flash Layer:
New "stellaris recover" command, implements the procedure
to recover locked devices (restoring non-volatile
state to the factory defaults, including erasing
the flash and its protection bits, and possibly
re-enabling hardware debugging).
PIC32MX now uses algorithm for flash programming, this
has increased the performance by approx 96%.
New 'pic32mx unlock' cmd to remove readout protection.
New STM32 Value Line Support.
New 'virtual' flash driver, used to associate other addresses
with a flash bank. See pic32mx.cfg for usage.
New iMX27 NAND flash controller driver.
Board, Target, and Interface Configuration Scripts:
Support IAR LPC1768 kickstart board (by Olimex)
Support Voipac PXA270/PXA270M module.
New $PARPORTADDR tcl variable used to change default
parallel port address used.
Remove lm3s811.cfg; use "stellaris.cfg" instead
Core Jim/TCL Scripting:
New "add_script_search_dir" command, behaviour is the same
as the "-s" cmd line option.
Documentation:
Build and Release:
For more details about what has changed since the last release,
see the git repository history. With gitweb, you can browse that
in various levels of detail.
For older NEWS, see the NEWS files associated with each release
(i.e. NEWS-<version>).
For more information about contributing test reports, bug fixes, or new
features and device support, please read the new Developer Manual (or
the BUGS and PATCHES.txt files in the source archive).

54
NEWS-0.6.0
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This file includes highlights of the changes made in the
OpenOCD source archive release. See the
repository history for details about what changed, including
bugfixes and other issues not mentioned here.
JTAG Layer:
New STLINK V1/V2 JTAG/SWD adapter support.
New OSJTAG adapter support.
New Tincantools Flyswatter2 support.
Improved ULINK driver.
Improved RLINK driver.
Support for adapters based on FT232H chips.
New experimental driver for FTDI based adapters, using libusb-1.0 in asynchronous mode.
Boundary Scan:
Target Layer:
New Cortex-M0 support.
New Cortex-M4 support.
Improved Working area algorithm.
New RTOS support. Currently linux, FreeRTOS, ThreadX and eCos.
Connecting under reset to Cortex-Mx and MIPS chips.
Flash Layer:
New SST39WF1601 support.
New EN29LV800BB support.
New async algorithm support for selected targets, stm32, stellaris and pic32.
New Atmel SAM3S, SAM3N support.
New ST STM32L support.
New Microchip PIC32MX1xx/2xx support.
New Freescale Kinetis K40 support.
Board, Target, and Interface Configuration Scripts:
Support Dangerous Prototypes Bus Blaster.
Support ST SPEAr Family.
Support Gumstix Verdex boards.
Support TI Beaglebone.
Documentation:
Improved HACKING info for submitting patches.
Fixed numerous broken links.
Build and Release:
For more details about what has changed since the last release,
see the git repository history. With gitweb, you can browse that
in various levels of detail.
For older NEWS, see the NEWS files associated with each release
(i.e. NEWS-<version>).
For more information about contributing test reports, bug fixes, or new
features and device support, please read the new Developer Manual (or
the BUGS and PATCHES.txt files in the source archive).

43
NEWS-0.7.0
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This file includes highlights of the changes made in the
OpenOCD source archive release. See the
repository history for details about what changed, including
bugfixes and other issues not mentioned here.
JTAG Layer:
New TI ICDI adapter support.
Support Latest OSBDM firmware.
Improved MIPS EJTAG Support.
Boundary Scan:
Target Layer:
New ARMv7R and Cortex-R4 support.
Added ChibiOS/RT support.
Flash Layer:
New NXP LPC1850 support.
New NXP LPC4300 support.
New NXP SPIFI support.
New Energy Micro EFM32 support.
New ST STM32W support.
New ST STM32f2 write protection and lock/unlock support.
Ability to override STM32 flash bank size.
Board, Target, and Interface Configuration Scripts:
Support Freescale i.MX6 series targets.
Documentation:
New MIPS debugging info.
Build and Release:
For more details about what has changed since the last release,
see the git repository history. With gitweb, you can browse that
in various levels of detail.
For older NEWS, see the NEWS files associated with each release
(i.e. NEWS-<version>).
For more information about contributing test reports, bug fixes, or new
features and device support, please read the new Developer Manual (or
the BUGS and PATCHES.txt files in the source archive).

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NEWS-0.8.0
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This file includes highlights of the changes made in the OpenOCD
source archive release.
JTAG Layer:
* New CMSIS-DAP driver
* Andes AICE debug adapter support
* New OpenJTAG driver
* New BCM2835 (RaspberryPi) driver
* JTAG VPI client driver (for OpenRISC Reference Platform SoC)
* Xilinx BSCAN_* for OpenRISC support
* ST-LINKv2-1 support
* ST-LINKv2 SWO tracing support (UART emulation)
* JLink-OB (onboard) support
* Altera USB Blaster driver rewrite, initial Blaster II
support
* ULINK driver ported to libusb-1.0, OpenULINK build fixes
* Support up to 64 bit IR lengths
* SVF playback (FPGA programming) fixes
* "ftdi" interface driver got extensive testing and is now
recommended over the old ft2232 implementation
Boundary Scan:
Target Layer:
* New target: Andes nds32
* New target: OpenRISC OR1K
* New target: Intel Quark X10xx
* MIPS EJTAG 1.5/2.0 support
* MIPS speed improvements
* Cortex-M, Cortex-A (MEM-AP, APB-AP) targets working with BE
hosts now
* XScale vector_catch support, reset fixes
* dsp563xx ad-hoc breakpoint/watchpoint support
* RTOS support for embKernel
* Target profiling improvements
* Memory access functions testbench
Flash Layer:
* STM32 family sync with reference manuals, other bugfixes
* STM32F401, STM32F07x support
* Atmel SAM4L, SAMG5x support
* at91sam3sd8{a,b}, at91sam3s8{a,b,c}, at91sam4s,
at91sam3n0{a,b,0a,0b} support, bugfixes
* Atmel SAMD support
* Milandr 1986ВЕ* support
* Kinetis KL, K21 support
* Nuvoton NuMicro MINI5{1,2,4} support
* Nuvoton NUC910 series support
* NXP LPC43xx, LPC2000 fixes
* NXP LPC800, LPC810 support
* More ATmega parts supported
* Fujitsu MB9Ax family support
* EFM32 Wonder Gecko family support
* Nordic nRF51 support
Board, Target, and Interface Configuration Scripts:
* STM32W108xx generic target config
* STM32F429 discovery board config
* STM32 Nucleo boards configs
* DENX M53EVK board config
* Altera Cyclone V SoC, SoCkit config
* New TI Launchpads board configs
* TI am43xx devices, AM437x GP EVM, AM438x ePOS EVM board
configs
* Marvell Armada 370 family initial support
* TI TMDX570LS31USB (TMS570, Cortex-R4) support scripts
* Freescale FRDM-KL25Z, KL46Z board configs
* Digilent Zedboard config
* Asus RT-N16, Linksys WRT54GL, BT HomeHub board configs
* Atmel Xplained initial support
* Broadcom bcm28155_ap board config
* TUMPA, TUMPA Lite interface configs
* Digilent JTAG-SMT2 interface config
* New RAM testing functions
* Easy-to-use firmware recovery helpers targetting ordinary
users with common equipment
Server Layer:
* Auto-generation of GDB target description for ARMv7-M,
ARM4, nds32, OR1K, Quark
* GDB File-I/O Remote Protocol extension support
* Default GDB flashing events handlers to initialise and reset
the target automatically when "load" is used
Documentation:
* Extensive README* changes
* The official User's Guide was proofread
* Example cross-build script
* RTOS documentation improvements
* Tcl RPC documentation and examples added
Build and Release:
* *BSD, OS X, clang, ARM, windows build fixes
* New pkg-config support changes the way libusb (and other
dependencies) are handled. Many adapter drivers are now
selected automatically during the configure stage.
This release also contains a number of other important functional and
cosmetic bugfixes. For more details about what has changed since the
last release, see the git repository history:
http://sourceforge.net/p/openocd/code/ci/v0.8.0/log/?path=
For older NEWS, see the NEWS files associated with each release
(i.e. NEWS-<version>).
For more information about contributing test reports, bug fixes, or new
features and device support, please read the new Developer Manual (or
the BUGS and PATCHES.txt files in the source archive).

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NEWS-0.9.0
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This file includes highlights of the changes made in the OpenOCD
source archive release.
JTAG Layer:
* SWD support with FTDI, Versaloon, J-Link, sysfsgpio
* CMSIS-DAP massive speed and stability improvements
* Versaloon driver ported to libusb-1.0
* STLink can reestablish communication with a target that was
disconnected or rebooted
* STLink FAULT and WAIT SWD handling improved
* New hla_serial command to distinguish between several HLA
adapters attached to a single machine
* Serial number support for CMSIS-DAP and J-Link adapters
* Support for more J-Link adapters
* TAP autoprobing improvements
* Big speedup for SVF playback with USB Blaster
Boundary Scan:
Target Layer:
* Stability improvements for targets that get disconnected or
rebooted during a debug session
* MIPS speed and reliability improvements
* MIPS 1.5/2.0 fixes
* ARMv7-R improvements
* Cortex-A improvements, A7, A15 MPCores support
* FPU support for ARMv7-M (Cortex-M4F)
* TPIU/ITM support (including SWO/SWV tracing), can be
captured with external tools or STLink
* JTAG Serial Port (Advanced Debug System softcore) support
* Profiling support for OpenRISC
* ChibiOS/RT 3.0 support (with and without FPU)
* FreeRTOS current versions support
* Freescale MQX RTOS support
* GDB target description support for MIPS
* The last created target is auto-selected as the current
Flash Layer:
* nRF51 async loader to improve flashing performance and stability
* Cypress PSoC 41xx/42xx and CCG1 families flash driver
* Silabs SiM3 family flash driver
* Marvell Wireless Microcontroller SPI flash driver
* Kinetis mass erase (part unsecuring) implemented
* lpcspifi stability fixes
* STM32 family sync with reference manuals, L0 support, bugfixes
* LPC2000 driver automatically determines part and flash size
* NXP LPC11(x)xx, LPC13xx, LPC15xx, LPC8xx, LPC5410x, LPC407x support
* Atmel SAMD, SAMR, SAML21 devices support
* Atmel SAM4E16 support
* ZeroGecko family support
* TI Tiva C Blizzard and Snowflake families support
* Nuvoton NuMicro M051 support
* EZR32 support in EFM32 driver
Board, Target, and Interface Configuration Scripts:
* Normal target configs can work with HLA (STLink, ICDI) adapters
* STM32 discovery and Nucleo boards configs
* Gumstix AeroCore board config
* General Plus GP326XXXA target config
* Micrel KS869x target config
* ASUS RT-N66U board config
* Atmel SAM4E-EK board config
* Atmel AT91SAM4L proper reset handling implemented
* TI OMAP/AM 3505, 3517 target configs
* nRF51822-mKIT board config
* RC Module К1879ХБ1Я target config
* TI TMDX570LS20SUSB board config
* TI TMS570 USB Kit board config
* TI CC2538, CC26xx target configs
* TI AM437x major config improvements, DDR support
* TI AM437X IDK board config
* TI SimpleLink Wi-Fi CC3200 LaunchPad configs
* Silicon Labs EM357, EM358 target configs
* Infineon XMC1000, XMC4000 family targets and boards configs
* Atheros AR9331 target config
* TP-LINK TL-MR3020 board config
* Alphascale asm9260t target and eval kit configs
* Olimex SAM7-LA2 (AT91SAM7A2) board config
* EFM32 Gecko boards configs
* Spansion FM4 target and SK-FM4-176L-S6E2CC board configs
* LPC1xxx target configs were restructured
* IoT-LAB debug adapter config
* DP BusBlaster KT-Link compatible config
Server Layer:
* Polling period can be configured
* "shutdown" command has an immediate effect
* The "program" command doesn't lead to a shutdown by
default, use optional "exit" parameter for the old behaviour
* Proper OS signal handling was implemented
* Async target notifications for the Tcl RPC
Documentation:
Build and Release:
This release also contains a number of other important functional and
cosmetic bugfixes. For more details about what has changed since the
last release, see the git repository history:
http://sourceforge.net/p/openocd/code/ci/v0.9.0/log/?path=
For older NEWS, see the NEWS files associated with each release
(i.e. NEWS-<version>).
For more information about contributing test reports, bug fixes, or new
features and device support, please read the new Developer Manual (or
the BUGS and PATCHES.txt files in the source archive).

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Reporting Unknown JTAG TAP IDS
------------------------------
If OpenOCD reports an UNKNOWN or Unexpected Tap ID please report it to
the development mailing list - However - keep reading.
openocd-devel@lists.sourceforge.net.
========================================
About "UNEXPECTED" tap ids.
Before reporting an "UNEXPECTED TAP ID" - take a closer look.
Perhaps you have your OpenOCD configured the wrong way, maybe you
have the tap configured the wrong way? Or something else is wrong.
(Remember: OpenOCD does not stop if the tap is not present)
This "tap id check" is there for a purpose.
The goal is to help get the *right* configuration.
The idea is this:
Every JTAG tap is suppose to have "a unique 32bit tap id" number.
They are suppose to be "sort of unique" but they are not. There are
no guarantees.
Version Number Changes:
Sometimes, the tap ID only differs by VERSION number. If so - it's
not a big deal. Please do report this information. We'd like to
know about it.
For example
Error: ERROR: Tap: s3c4510.cpu - Expected id: 0x3f0f0f0f, Got: 0x1f0f0f0f
Error: ERROR: expected: mfg: 0x787, part: 0xf0f0, ver: 0x3
Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x1
========================================
Updating the Tap ID number your self
Why do this? You just want the warning to go away. And don't want
to update your version/instance of OpenOCD.
On simple systems, to fix this problem, in your "openocd.cfg" file,
override the tap id. Depending on the tap, add one of these 3
commands:
set CPUTAPID newvalue
or set BSTAPID newvalue
or set FLASHTAPID newvalue
or set ETMTAPID newvalue
Where "newvalue" is the new value you are seeing.
On complex systems, (with many taps and chips) you probably have a
custom configuration file. Its is more complicated, you're going to
have to read through the configuration files
========================================
What to send:
Cut & paste the output of OpenOCD that pointed you at this file.
Please include the VERSION number of OpenOCD you are using.
And please include the information below.
========================================
A) The JTAG TAP ID code.
This is always a 32bit hex number.
Examples:
0x1f0f0f0f - is an old ARM7TDMI
0x3f0f0f0f - is a newer ARM7TDMI
0x3ba00477 - is an ARM Cortex-M3
Some chips have multiple JTAG taps - be sure to list
each one individually - ORDER is important!
========================================
B) The maker of the part
Examples:
Xilinx, Atmel, ST Micro Systems, Freescale
========================================
C) The family of parts it belongs to
Examples:
"NXP LPC Series"
"Atmel SAM7 Series"
========================================
D) The actual part number on the package
For example: "S3C45101x01"
========================================
E) What type of board it is.
ie: a "commercial off the self eval board" that one can purchase (as
opposed to your private internal custom board)
For example: ST Micro systems has Eval boards, so does Analog Devices
Or - if it is inside something "hackers like to hack" that information
is helpful too.
For example: A consumer GPS unit or a cellphone
========================================
(F) The maker of the board
ie: Olimex, LogicPD, Freescale(eval board)
========================================
(G) Identifying information on the board.
Not good: "iar red ST eval board"
Really good: "IAR STR912-SK evaluation board"
========================================
(H) Are there other interesting (JTAG) chips on the board?
ie: An FPGA or CPLD ...
========================================
(I) What target config files need updating?
In fact it's best if you submit a patch with those
updates. Most of the other information listed here
is just to help create a good patch.
========================================

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Welcome to OpenOCD!
===================
OpenOCD provides on-chip programming and debugging support with a
layered architecture of JTAG interface and TAP support including:
- (X)SVF playback to faciliate automated boundary scan and FPGA/CPLD
programming;
- debug target support (e.g. ARM, MIPS): single-stepping,
breakpoints/watchpoints, gprof profiling, etc;
- flash chip drivers (e.g. CFI, NAND, internal flash);
- embedded TCL interpreter for easy scripting.
Several network interfaces are available for interacting with OpenOCD:
telnet, TCL, and GDB. The GDB server enables OpenOCD to function as a
"remote target" for source-level debugging of embedded systems using
the GNU GDB program (and the others who talk GDB protocol, e.g. IDA
Pro).
This README file contains an overview of the following topics:
- quickstart instructions,
- how to find and build more OpenOCD documentation,
- list of the supported hardware,
- the installation and build process,
- packaging tips.
============================
Quickstart for the impatient
============================
If you have a popular board then just start OpenOCD with its config,
e.g.:
openocd -f board/stm32f4discovery.cfg
If you are connecting a particular adapter with some specific target,
you need to source both the jtag interface and the target configs,
e.g.:
openocd -f interface/ftdi/jtagkey2.cfg -c "transport select jtag" \
-f target/ti_calypso.cfg
openocd -f interface/stlink-v2-1.cfg -c "transport select hla_swd" \
-f target/stm32l0.cfg
NB: when using an FTDI-based adapter you should prefer configs in the
ftdi directory; the old configs for the ft2232 are deprecated.
After OpenOCD startup, connect GDB with
(gdb) target extended-remote localhost:3333
=====================
OpenOCD Documentation
=====================
In addition to the in-tree documentation, the latest manuals may be
viewed online at the following URLs:
OpenOCD User's Guide:
http://openocd.org/doc/html/index.html
OpenOCD Developer's Manual:
http://openocd.org/doc/doxygen/html/index.html
These reflect the latest development versions, so the following section
introduces how to build the complete documentation from the package.
For more information, refer to these documents or contact the developers
by subscribing to the OpenOCD developer mailing list:
openocd-devel@lists.sourceforge.net
Building the OpenOCD Documentation
----------------------------------
By default the OpenOCD build process prepares documentation in the
"Info format" and installs it the standard way, so that "info openocd"
can access it.
Additionally, the OpenOCD User's Guide can be produced in the
following different formats:
# If PDFVIEWER is set, this creates and views the PDF User Guide.
make pdf && ${PDFVIEWER} doc/openocd.pdf
# If HTMLVIEWER is set, this creates and views the HTML User Guide.
make html && ${HTMLVIEWER} doc/openocd.html/index.html
The OpenOCD Developer Manual contains information about the internal
architecture and other details about the code:
# NB! make sure doxygen is installed, type doxygen --version
make doxygen && ${HTMLVIEWER} doxygen/index.html
==================
Supported hardware
==================
JTAG adapters
-------------
AICE, ARM-JTAG-EW, ARM-USB-OCD, ARM-USB-TINY, AT91RM9200, axm0432,
BCM2835, Bus Blaster, Buspirate, Chameleon, CMSIS-DAP, Cortino, DENX,
Digilent JTAG-SMT2, DLC 5, DLP-USB1232H, embedded projects, eStick,
FlashLINK, FlossJTAG, Flyswatter, Flyswatter2, Gateworks, Hoegl, ICDI,
ICEBear, J-Link, JTAG VPI, JTAGkey, JTAGkey2, JTAG-lock-pick, KT-Link,
Lisa/L, LPC1768-Stick, MiniModule, NGX, NXHX, OOCDLink, Opendous,
OpenJTAG, Openmoko, OpenRD, OSBDM, Presto, Redbee, RLink, SheevaPlug
devkit, Stellaris evkits, ST-LINK (SWO tracing supported),
STM32-PerformanceStick, STR9-comStick, sysfsgpio, TUMPA, Turtelizer,
ULINK, USB-A9260, USB-Blaster, USB-JTAG, USBprog, VPACLink, VSLLink,
Wiggler, XDS100v2, Xverve.
Debug targets
-------------
ARM11, ARM7, ARM9, AVR32, Cortex-A, Cortex-R, Cortex-M, LS102x-SAP,
Feroceon/Dragonite, DSP563xx, DSP5680xx, FA526, MIPS EJTAG, NDS32,
XScale, Intel Quark.
Flash drivers
-------------
ADUC702x, AT91SAM, AVR, CFI, DSP5680xx, EFM32, EM357, FM3, FM4, Kinetis,
LPC8xx/LPC1xxx/LPC2xxx/LPC541xx, LPC2900, LPCSPIFI, Marvell QSPI,
Milandr, NIIET, NuMicro, PIC32mx, PSoC4, SiM3x, Stellaris, STM32, STMSMI,
STR7x, STR9x, nRF51; NAND controllers of AT91SAM9, LPC3180, LPC32xx,
i.MX31, MXC, NUC910, Orion/Kirkwood, S3C24xx, S3C6400, XMC1xxx, XMC4xxx.
==================
Installing OpenOCD
==================
A Note to OpenOCD Users
-----------------------
If you would rather be working "with" OpenOCD rather than "on" it, your
operating system or JTAG interface supplier may provide binaries for
you in a convenient-enough package.
Such packages may be more stable than git mainline, where
bleeding-edge development takes place. These "Packagers" produce
binary releases of OpenOCD after the developers produces new "release"
versions of the source code. Previous versions of OpenOCD cannot be
used to diagnose problems with the current release, so users are
encouraged to keep in contact with their distribution package
maintainers or interface vendors to ensure suitable upgrades appear
regularly.
Users of these binary versions of OpenOCD must contact their Packager to
ask for support or newer versions of the binaries; the OpenOCD
developers do not support packages directly.
A Note to OpenOCD Packagers
---------------------------
You are a PACKAGER of OpenOCD if you:
- Sell dongles and include pre-built binaries;
- Supply tools or IDEs (a development solution integrating OpenOCD);
- Build packages (e.g. RPM or DEB files for a GNU/Linux distribution).
As a PACKAGER, you will experience first reports of most issues.
When you fix those problems for your users, your solution may help
prevent hundreds (if not thousands) of other questions from other users.
If something does not work for you, please work to inform the OpenOCD
developers know how to improve the system or documentation to avoid
future problems, and follow-up to help us ensure the issue will be fully
resolved in our future releases.
That said, the OpenOCD developers would also like you to follow a few
suggestions:
- Send patches, including config files, upstream, participate in the
discussions;
- Enable all the options OpenOCD supports, even those unrelated to your
particular hardware;
- Use "ftdi" interface adapter driver for the FTDI-based devices.
As a PACKAGER, never link against the FTD2XX library, as the resulting
binaries can't be legally distributed, due to the restrictions of the
GPL.
================
Building OpenOCD
================
The INSTALL file contains generic instructions for running 'configure'
and compiling the OpenOCD source code. That file is provided by
default for all GNU autotools packages. If you are not familiar with
the GNU autotools, then you should read those instructions first.
The remainder of this document tries to provide some instructions for
those looking for a quick-install.
OpenOCD Dependencies
--------------------
GCC or Clang is currently required to build OpenOCD. The developers
have begun to enforce strict code warnings (-Wall, -Werror, -Wextra,
and more) and use C99-specific features: inline functions, named
initializers, mixing declarations with code, and other tricks. While
it may be possible to use other compilers, they must be somewhat
modern and could require extending support to conditionally remove
GCC-specific extensions.
You'll also need:
- make
- libtool
- pkg-config >= 0.23 (or compatible)
Additionally, for building from git:
- autoconf >= 2.64
- automake >= 1.9
- texinfo
USB-based adapters depend on libusb-1.0 and some older drivers require
libusb-0.1 or libusb-compat-0.1. A compatible implementation, such as
FreeBSD's, additionally needs the corresponding .pc files.
USB-Blaster, ASIX Presto, OpenJTAG and ft2232 interface adapter
drivers need either one of:
- libftdi: http://www.intra2net.com/en/developer/libftdi/index.php
- ftd2xx: http://www.ftdichip.com/Drivers/D2XX.htm (proprietary,
GPL-incompatible)
CMSIS-DAP support needs HIDAPI library.
Permissions delegation
----------------------
Running OpenOCD with root/administrative permissions is strongly
discouraged for security reasons.
For USB devices on GNU/Linux you should use the contrib/99-openocd.rules
file. It probably belongs somewhere in /etc/udev/rules.d, but
consult your operating system documentation to be sure. Do not forget
to add yourself to the "plugdev" group.
For parallel port adapters on GNU/Linux and FreeBSD please change your
"ppdev" (parport* or ppi*) device node permissions accordingly.
For parport adapters on Windows you need to run install_giveio.bat
(it's also possible to use "ioperm" with Cygwin instead) to give
ordinary users permissions for accessing the "LPT" registers directly.
Compiling OpenOCD
-----------------
To build OpenOCD, use the following sequence of commands:
./bootstrap (when building from the git repository)
./configure [options]
make
sudo make install
The 'configure' step generates the Makefiles required to build
OpenOCD, usually with one or more options provided to it. The first
'make' step will build OpenOCD and place the final executable in
'./src/'. The final (optional) step, ``make install'', places all of
the files in the required location.
To see the list of all the supported options, run
./configure --help
Cross-compiling Options
-----------------------
Cross-compiling is supported the standard autotools way, you just need
to specify the cross-compiling target triplet in the --host option,
e.g. for cross-building for Windows 32-bit with MinGW on Debian:
./configure --host=i686-w64-mingw32 [options]
To make pkg-config work nicely for cross-compiling, you might need an
additional wrapper script as described at
http://www.flameeyes.eu/autotools-mythbuster/pkgconfig/cross-compiling.html
This is needed to tell pkg-config where to look for the target
libraries that OpenOCD depends on. Alternatively, you can specify
*_CFLAGS and *_LIBS environment variables directly, see "./configure
--help" for the details.
Parallel Port Dongles
---------------------
If you want to access the parallel port using the PPDEV interface you
have to specify both --enable-parport AND --enable-parport-ppdev, since the
the later option is an option to the parport driver.
The same is true for the --enable-parport-giveio option, you have to
use both the --enable-parport AND the --enable-parport-giveio option
if you want to use giveio instead of ioperm parallel port access
method.
Using FTDI's FTD2XX
-------------------
The (closed source) FTDICHIP.COM solution is faster than libftdi on
Windows. That is the motivation for supporting it even though its
licensing restricts it to non-redistributable OpenOCD binaries, and it
is not available for all operating systems used with OpenOCD. You may,
however, build such copies for personal use.
The FTDICHIP drivers come as either a (win32) ZIP file, or a (Linux)
TAR.GZ file. You must unpack them ``some where'' convenient. As of this
writing FTDICHIP does not supply means to install these files "in an
appropriate place."
You should use the following ./configure options to make use of
FTD2XX:
--with-ftd2xx-win32-zipdir
Where (CYGWIN/MINGW) the zip file from ftdichip.com
was unpacked <default=search>
--with-ftd2xx-linux-tardir
Where (Linux/Unix) the tar file from ftdichip.com
was unpacked <default=search>
--with-ftd2xx-lib=(static|shared)
Use static or shared ftd2xx libs (default is static)
Remember, this library is binary-only, while OpenOCD is licenced
according to GNU GPLv2 without any exceptions. That means that
_distributing_ copies of OpenOCD built with the FTDI code would
violate the OpenOCD licensing terms.
Note that on Linux there is no good reason to use these FTDI binaries;
they are no faster (on Linux) than libftdi, and cause licensing issues.
==========================
Obtaining OpenOCD From GIT
==========================
You can download the current GIT version with a GIT client of your
choice from the main repository:
git://git.code.sf.net/p/openocd/code
You may prefer to use a mirror:
http://repo.or.cz/r/openocd.git
git://repo.or.cz/openocd.git
Using the GIT command line client, you might use the following command
to set up a local copy of the current repository (make sure there is no
directory called "openocd" in the current directory):
git clone git://git.code.sf.net/p/openocd/code openocd
Then you can update that at your convenience using
git pull
There is also a gitweb interface, which you can use either to browse
the repository or to download arbitrary snapshots using HTTP:
http://repo.or.cz/w/openocd.git
Snapshots are compressed tarballs of the source tree, about 1.3 MBytes
each at this writing.

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Building OpenOCD for OSX
------------------------
There are a few prerequisites you will need first:
- Xcode 5 (install from the AppStore)
- Command Line Tools (install from Xcode 5 -> Preferences -> Downloads)
- Gentoo Prefix (http://www.gentoo.org/proj/en/gentoo-alt/prefix/bootstrap.xml)
or
- Homebrew (http://mxcl.github.io/homebrew/)
or
- MacPorts (http://www.macports.org/install.php)
With Gentoo Prefix you can build the release version or the latest
devel version (-9999) the usual way described in the Gentoo
documentation. Alternatively, install the prerequisites and build
manually from the sources.
With Homebrew you can either run:
brew install [--HEAD] openocd (where optional --HEAD asks brew to
install the current git version)
or
brew install libtool automake libusb [libusb-compat] [hidapi] [libftdi]
(to install the needed dependencies and then proceed with the
manual building procedure)
For building with MacPorts you need to run:
sudo port install libtool automake autoconf pkgconfig \
libusb [libusb-compat] [libftdi1]
You should also specify LDFLAGS and CPPFLAGS to allow configure to use
MacPorts' libraries, so run configure like this:
LDFLAGS=-L/opt/local/lib CPPFLAGS=-I/opt/local/include ./configure [options]
See README for the generic building instructions.
If you're using a USB adapter and have a driver kext matched to it,
you will need to unload it prior to running OpenOCD. E.g. with Apple
driver (OS X 10.9 or later) for FTDI run:
sudo kextunload -b com.apple.driver.AppleUSBFTDI
for FTDI vendor driver use:
sudo kextunload FTDIUSBSerialDriver.kext
To learn more on the topic please refer to the official libusb FAQ:
https://github.com/libusb/libusb/wiki/FAQ

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Building OpenOCD for Windows
----------------------------
You can build OpenOCD for Windows natively with either MinGW-w64/MSYS
or Cygwin (plain MinGW might work with --disable-werror but is not
recommended as it doesn't provide enough C99 compatibility).
Alternatively, one can cross-compile it using MinGW-w64 on a *nix
host. See README for the generic instructions.
Also, the MSYS2 project provides both ready-made binaries and an easy
way to self-compile from their software repository out of the box.
Native MinGW-w64/MSYS compilation
-----------------------------
As MSYS doesn't come with pkg-config pre-installed, you need to add it
manually. The easiest way to do that is to download pkg-config-lite
from:
http://sourceforge.net/projects/pkgconfiglite/
Then simply unzip the archive to the root directory of your MinGW-w64
installation.
USB adapters
------------
For the adapters that use a HID-based protocol, e.g. CMSIS-DAP, you do
not need to perform any additional configuration.
For all the others you usually need to have WinUSB.sys (or
libusbK.sys) driver installed. Some vendor software (e.g. for
ST-LINKv2) does it on its own. For the other cases the easiest way to
assign WinUSB to a device is to use the latest Zadig installer:
http://zadig.akeo.ie
When using a composite USB device, it's often necessary to assign
WinUSB.sys to the composite parent instead of the specific
interface. To do that one needs to activate an advanced option in the
Zadig installer.
For the old drivers that use libusb-0.1 API you might need to link
against libusb-win32 headers and install the corresponding driver with
Zadig.
If you need to use the same adapter with other applications that may
require another driver, a solution for Windows Vista and above is to
activate the IgnoreHWSerNum registry setting for the USB device.
That setting forces Windows to associate the driver per port instead of
per serial number, the same behaviour as when the device does not contain
a serial number. So different drivers can be installed for the adapter on
different ports and you just need to plug the adapter into the correct
port depending on which application to use.
For more information, see:
http://msdn.microsoft.com/en-us/library/windows/hardware/jj649944(v=vs.85).aspx
http://www.ftdichip.com/Support/Knowledgebase/index.html?ignorehardwareserialnumber.htm

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// This file is part of the Doxygen Developer Manual
/** @page tasks Pending and Open Tasks
This page lists pending and open tasks being considered or worked upon
by the OpenOCD community.
@section thelist The List
Most items are open for the taking, but please post to the mailing list
before spending much time working on anything lists here. The community
may have evolved an idea since it was added here.
Feel free to send patches to add or clarify items on this list, too.
@section thelisttcl TCL
This section provides possible things to improve with OpenOCD's TCL support.
- Fix problem with incorrect line numbers reported for a syntax
error in a reset init event.
- organize the TCL configurations:
- provide more directory structure for boards/targets?
- factor configurations into layers (encapsulation and re-use)
- Fix handling of variables between multiple command line "-c" and "-f"
parameters. Currently variables assigned through one such parameter
command/script are unset before the next one is invoked.
- Isolate all TCL command support:
- Pure C CLI implementations using --disable-builtin-tcl.
- Allow developers to build new dongles using OpenOCD's JTAG core.
- At first, provide only low-level JTAG support; target layer and
above rely heavily on scripting event mechanisms.
- Allow full TCL support? add --with-tcl=/path/to/installed/tcl
- Move TCL support out of foo.[ch] and into foo_tcl.[ch] (other ideas?)
- See src/jtag/core.c and src/jtag/tcl.c for an example.
- allow some of these TCL command modules to be dynamically loadable?
@section thelistjtag JTAG
This section list issues that need to be resolved in the JTAG layer.
@subsection thelistjtagcore JTAG Core
The following tasks have been suggested for cleaning up the JTAG layer:
- use tap_set_state everywhere to allow logging TAP state transitions
- Encapsulate cmd_queue_cur_state and related variable handling.
- add slick 32 bit versions of jtag_add_xxx_scan() that avoids
buf_set_u32() calls and other evidence of poor impedance match between
API and calling code. New API should cut down # of lines in calling
code by 100's and make things clearer. Also potentially be supported
directly in minidriver API for better embedded host performance.
The following tasks have been suggested for adding new core JTAG support:
- Improve autodetection of TAPs by supporting tcl escape procedures that
can configure discovered TAPs based on IDCODE value ... they could:
- Remove guessing for irlen
- Allow non-default irmask/ircapture values
- SPI/UART emulation:
- (ab)use bit-banging JTAG interfaces to emulate SPI/UART
- allow SPI to program flash, MCUs, etc.
@subsection thelistjtaginterfaces JTAG Interfaces
There are some known bugs to fix in JTAG adapter drivers:
- For JTAG_STATEMOVE to TAP_RESET, all drivers must ignore the current
recorded state. The tap_get_state() call won't necessarily return
the correct value, especially at server startup. Fix is easy: in
that case, always issue five clocks with TMS high.
- amt_jtagaccel.c
- arm-jtag-ew.c
- bitbang.c
- bitq.c
- gw16012.c
- jlink.c
- usbprog.c
- vsllink.c
- rlink/rlink.c
- bug: USBprog is broken with new tms sequence; it needs 7-clock cycles.
Fix promised from Peter Denison openwrt at marshadder.org
Workaround: use "tms_sequence long" @par
https://lists.berlios.de/pipermail/openocd-development/2009-July/009426.html
The following tasks have been suggested for improving OpenOCD's JTAG
interface support:
- rework USB communication to be more robust. Two possible options are:
-# use libusb-1.0.1 with libusb-compat-0.1.1 (non-blocking I/O wrapper)
-# rewrite implementation to use non-blocking I/O
- J-Link driver:
- fix to work with long scan chains, such as R.Doss's svf test.
- FT2232 (libftdi):
- make performance comparable to alternatives (on Win32, D2XX is faster)
- make usability comparable to alternatives
- Autodetect USB based adapters; this should be easy on Linux. If there's
more than one, list the options; otherwise, just select that one.
The following tasks have been suggested for adding new JTAG interfaces:
- TCP driver: allow client/server for remote JTAG interface control.
This requires a client and a server. The server is built into the
normal OpenOCD and takes commands from the client and executes
them on the interface returning the result of TCP/IP. The client
is an OpenOCD which is built with a TCP/IP minidriver. The use
of a minidriver is required to capture all the jtag_add_xxx()
fn's at a high enough level and repackage these cmd's as
TCP/IP packets handled by the server.
@section thelistswd Serial Wire Debug
- implement Serial Wire Debug interface
@section thelistbs Boundary Scan Support
- add STAPL support?
- add BSDL support?
A few possible options for the above:
-# Fake a TCL equivalent?
-# Integrate an existing library?
-# Write a new C implementation a la Jim?
Once the above are completed:
- add support for programming flash using boundary scan techniques
- add integration with a modified gerber view program:
- provide means to view the PCB and select pins and traces
- allow use-cases such as the following:
- @b Stimulus
-# Double-click on a pin (or trace) with the mouse.
- @b Effects
-# The trace starts blinking, and
-# OpenOCD toggles the pin(s) 0/1.
@section thelisttargets Target Support
- Many common ARM cores could be autodetected using IDCODE
- general layer cleanup: @par
https://lists.berlios.de/pipermail/openocd-development/2009-May/006590.html
- regression: "reset halt" between 729(works) and 788(fails): @par
https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
- registers
- add flush-value operation, call them all on resume/reset
- mcr/mrc target->type support
- missing from ARM920t, ARM966e, XScale.
It's possible that the current syntax is unable to support read-modify-write
operations(see arm966e).
- mcr/mrc - retire cp15 commands when there the mrc/mrc commands have been
tested from: arm926ejs, arm720t, cortex_a8
- ARM7/9:
- clean up "arm9tdmi vector_catch". Available for some arm7 cores? @par
https://lists.berlios.de/pipermail/openocd-development/2009-October/011488.html
https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html
- add reset option to allow programming embedded ice while srst is asserted.
Some CPUs will gate the JTAG clock when srst is asserted and in this case,
it is necessary to program embedded ice and then assert srst afterwards.
- ARM926EJS:
- reset run/halt/step is not robust; needs testing to map out problems.
- ARM11 improvements (MB?)
- add support for asserting srst to reset the core.
- Single stepping works, but should automatically
use hardware stepping if available.
- mdb can return garbage data if read byte operation fails for
a memory region(16 & 32 byte access modes may be supported). Is this
a bug in the .MX31 PDK init script? Try on i.MX31 PDK:
mdw 0xb80005f0 0x8, mdh 0xb80005f0 0x10, mdb 0xb80005f0 0x20. mdb returns
garabage.
- implement missing functionality (grep FNC_INFO_NOTIMPLEMENTED ...)
- Thumb2 single stepping: ARM1156T2 needs simulator support
- Cortex-A8 support (ML)
- add target implementation (ML)
- Cortex-M3 support
- when stepping, only write dirtied registers (be faster)
- when connecting to halted core, fetch registers (startup is quirky)
- Generic ARM run_algorithm() interface
- tagged struct wrapping ARM instructions and metadata
- not revision-specific (current: ARMv4+ARMv5 -or- ARMv6 -or- ARMv7)
- usable with at least arm_nandwrite() and generic CFI drivers
- ETM
- don't show FIFOFULL registers if they're not supported
- use comparators to get more breakpoints and watchpoints
- add "etm drivers" command
- trace driver init() via examine() paths only, not setup()/reset
- MC1322x support (JW/DE?)
- integrate and test support from JW (and DE?)
- get working with a known good interface (i.e. not today's jlink)
- AT91SAM92xx:
- improvements for unknown-board-atmel-at91sam9260.cfg (RD)
- STR9x: (ZW)
- improvements to str912.cfg to be more general purpose
- AVR: (SQ)
- independently verify implementation
- incrementally improve working prototype in trunk. (SQ)
- work out how to debug this target
- AVR debugging protocol.
- FPGA:
- Altera Nios Soft-CPU support
- Coldfire (suggested by NC)
- can we draw from the BDM project? @par
http://bdm.sourceforge.net/
or the OSBDM package @par
http://forums.freescale.com/freescale/board/message?board.id=OSBDM08&thread.id=422
@section thelistsvf SVF/XSVF
- develop SVF unit tests
- develop XSVF unit tests
@section thelistflash Flash Support
- finish documentation for the following flash drivers:
- avr
- pic32mx
- ocl
- str9xpec
- Don't expect writing all-ones to be a safe way to write without
changing bit values. Minimally it loses on flash modules with
internal ECC, where it may change the ECC.
- NOR flash_write_unlock() does that between sectors
- there may be other cases too
- Make sure all commands accept either a bank name or a bank number,
and be sure both identifiers show up in "flash banks" and "nand list".
Right now the user-friendly names are pretty much hidden...
@subsection thelistflashcfi CFI
- finish implementing bus width/chip width handling (suggested by NC)
- factor vendor-specific code into separate source files
- add new callback interface for vendor-specific code
- investigate/implement "thin wrapper" to use eCos CFI drivers (ØH)
@section thelistdebug Debugger Support
- add support for masks in watchpoints? @par
https://lists.berlios.de/pipermail/openocd-development/2009-October/011507.html
- breakpoints can get lost in some circumstances: @par
https://lists.berlios.de/pipermail/openocd-development/2009-June/008853.html
- add support for masks in watchpoints. The trick is that GDB does not
support a breakpoint mask in the remote protocol. One way to work around
this is to add a separate command "watchpoint_mask add/rem <addr> <mask>", that
is run to register a list of masks that the gdb_server knows to use with
a particular watchpoint address.
- integrate Keil AGDI interface to OpenOCD? (submitted by Dario Vecchio)
@section thelisttesting Testing Suite
This section includes several related groups of ideas:
- @ref thelistunittests
- @ref thelistsmoketests
- @ref thelisttestreports
- @ref thelisttestgenerichw
@subsection thelistunittests Unit Tests
- add testing skeleton to provide frameworks for adding tests
- implement server unit tests
- implement JTAG core unit tests
- implement JTAG interface unit tests
- implement flash unit tests
- implement target unit tests
@subsection thelistsmoketests Smoke Test Tools
-# extend 'make check' with a smoketest app
- checks for OOCD_TEST_CONFIG, etc. in environment (or config file)
- if properly set, runs the smoke test with specified parameters
- openocd -f ${OOCD_TEST_CONFIG}
- implies a modular test suite (see below)
- should be able to run some minimal tests with dummy interface:
- compare results of baseline sanity checks with expected results
-# builds a more complete test suite:
- existing testing/examples/ look like a great start
- all targets should be tested fully and for all capabilities
- we do NOT want a "lowest common denominator" test suite
- ... but can we start with one to get going?
- probably requires one test configuration file per board/target
- modularization can occur here, just like with targets/boards/chips
- coverage can increase over time, building up bundles of tests
-# add new 'smoketest' Makefile target:
- calls 'make check' (and the smoketest app)
- gather inputs and output into a report file
@subsection thelisttestreports Test Feedback Tools
These ideas were first introduced here: @par
https://lists.berlios.de/pipermail/openocd-development/2009-May/006358.html
- provide report submission scripts for e-mail and web forms
- add new Makefile targets to post the report:
- 'checkreportsend' -- send to list via e-mail (via sendmail)
- 'checkreportpost' -- send web form (via curl or other script)
@subsection thelisttestgenerichw Generic Hardware Tester
- implement VHDL to use for FPGA-based JTAG TAP testing device
- develop test suite that utilizes this testing device
@section thelistautotools Autotools Build System
- make entire configure process require less user consideration:
- automatically detect the features that are available, unless
options were specifically provided to configure
- provide a report of the drivers that will be build at the end of
running configure, so the users can verify which drivers will be
built during 'make' (and their options) .
- eliminate sources of confusion in @c bootstrap script:
-# Make @c bootstrap call 'configure --enable-maintainer-mode \<opts\>'?
-# Add @c buildstrap script to assist with bootstrap and configure steps.
- automatically build tool-chains required for cross-compiling
- produce mingw32, arm-elf, others using in-tree scripts
- build all required target code from sources
- make JTAG and USB debug output a run-time configuration option
@section thelistarchitecture Architectural Tasks
The following architectural tasks need to be accomplished and should be
fairly easy to complete:
- use dynamic allocations for working memory. Scan & fix code
for excessive stack allocations. take linux/scripts/checkstack.pl and
see what the worst offenders are. Dynamic stack allocations are found
at the bottom of the list below. Example, on amd64:
$ objdump -d | checkstack.pl | head -10
0x004311e3 image_open [openocd]: 13464
0x00431301 image_open [openocd]: 13464
0x004237a4 target_array2mem [openocd]: 4376
0x0042382b target_array2mem [openocd]: 4376
0x00423e74 target_mem2array [openocd]: 4360
0x00423ef9 target_mem2array [openocd]: 4360
0x00404aed handle_svf_command [openocd]: 2248
0x00404b7e handle_svf_command [openocd]: 2248
0x00413581 handle_flash_fill_command [openocd]: 2200
0x004135fa handle_flash_fill_command [openocd]: 2200
- clean-up code to match style guides
- factor code to eliminate duplicated functionality
- rewrite code that uses casts to access 16-bit and larger types
from unaligned memory addresses
- libopenocd support: @par
https://lists.berlios.de/pipermail/openocd-development/2009-May/006405.html
- review and clean up interface/target/flash APIs
The following strategic tasks will require ambition, knowledge, and time
to complete:
- overhaul use of types to improve 32/64-bit portability
- types for both host and target word sizes?
- can we use GDB's CORE_TYPE support?
- Allow N:M:P mapping of servers, targets, and interfaces
- loadable module support for interface/target/flash drivers and commands
- support both static and dynamic modules.
- should probably use libltdl for dynamic library handing.
@section thelistadmin Documentation Tasks
- Develop milestone and release guidelines, processes, and scripts.
- Develop "style" guidelines (and scripts) for maintainers:
- reviewing patches
- committing to git
- Review Users' Guide for documentation errors or omissions
- "capture" and "ocd_find" commands
- "ocd_" prefix on various stuff
- Update Developer's Manual (doxygen output)
- Add documentation describing the architecture of each module
- Provide more Technical Primers to bootstrap contributor knowledge
*/
/** @file
This file contains the @ref thelist page.
*/

43
bootstrap
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@ -1,43 +0,0 @@
#!/bin/sh
# Run the autotools bootstrap sequence to create the configure script
# Abort execution on error
set -e
if which libtoolize > /dev/null; then
libtoolize="libtoolize"
elif which glibtoolize >/dev/null; then
libtoolize="glibtoolize"
else
echo "$0: Error: libtool is required" >&2
exit 1
fi
if [ "$1" = "nosubmodule" ]; then
SKIP_SUBMODULE=1
elif [ -n "$1" ]; then
echo "$0: Illegal argument $1"
echo "USAGE: $0 [nosubmodule]"
exit 1
fi
# bootstrap the autotools
(
set -x
aclocal
${libtoolize} --automake --copy
autoconf
autoheader
automake --gnu --add-missing --copy
)
if [ -n "$SKIP_SUBMODULE" ]; then
echo "Skipping submodule setup"
else
echo "Setting up submodules"
git submodule init
git submodule update
fi
echo "Bootstrap complete. Quick build instructions:"
echo "./configure ...."

12
common.mk
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@ -1,12 +0,0 @@
# common flags used in openocd build
AM_CPPFLAGS = -I$(top_srcdir)/src \
-I$(top_builddir)/src \
-I$(top_srcdir)/src/helper \
-DPKGDATADIR=\"$(pkgdatadir)\" \
-DBINDIR=\"$(bindir)\"
if INTERNAL_JIMTCL
AM_CPPFLAGS += -I$(top_srcdir)/jimtcl \
-I$(top_builddir)/jimtcl
endif

26
config_subdir.m4
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@ -1,26 +0,0 @@
dnl
dnl If needed, define the m4_ifblank and m4_ifnblank macros from autoconf 2.64
dnl This allows us to run with earlier Autoconfs as well.
ifdef([m4_ifblank],[],[
m4_define([m4_ifblank],
[m4_if(m4_translit([[$1]], [ ][ ][
]), [], [$2], [$3])])])
dnl
ifdef([m4_ifnblank],[],[
m4_define([m4_ifnblank],
[m4_if(m4_translit([[$1]], [ ][ ][
]), [], [$3], [$2])])])
dnl
dnl AC_CONFIG_SUBDIRS does not allow configure options to be passed
dnl to subdirs, this function allows that by creating a configure.gnu
dnl script that prepends configure options and then calls the real
dnl configure script
AC_DEFUN([AX_CONFIG_SUBDIR_OPTION],
[
AC_CONFIG_SUBDIRS([$1])
m4_ifblank([$2], [rm -f $srcdir/$1/configure.gnu],
[echo -e '#!/bin/sh\nexec "`dirname "'\$'0"`/configure" $2 "'\$'@"' > "$srcdir/$1/configure.gnu"
])
])

1343
configure.ac
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File diff suppressed because it is too large Load Diff

134
contrib/99-openocd.rules
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@ -1,134 +0,0 @@
# Copy this file to /etc/udev/rules.d/
ACTION!="add|change", GOTO="openocd_rules_end"
SUBSYSTEM!="usb|tty|hidraw", GOTO="openocd_rules_end"
# Please keep this list sorted by VID:PID
# opendous and estick
ATTRS{idVendor}=="03eb", ATTRS{idProduct}=="204f", MODE="664", GROUP="plugdev"
# Original FT232/FT245 VID:PID
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6001", MODE="664", GROUP="plugdev"
# Original FT2232 VID:PID
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", MODE="664", GROUP="plugdev"
# Original FT4232 VID:PID
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6011", MODE="664", GROUP="plugdev"
# Original FT232H VID:PID
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6014", MODE="664", GROUP="plugdev"
# DISTORTEC JTAG-lock-pick Tiny 2
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="8220", MODE="664", GROUP="plugdev"
# TUMPA, TUMPA Lite
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="8a98", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="8a99", MODE="664", GROUP="plugdev"
# XDS100v2
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="a6d0", MODE="664", GROUP="plugdev"
# Xverve Signalyzer Tool (DT-USB-ST), Signalyzer LITE (DT-USB-SLITE)
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bca0", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bca1", MODE="664", GROUP="plugdev"
# TI/Luminary Stellaris Evaluation Board FTDI (several)
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bcd9", MODE="664", GROUP="plugdev"
# TI/Luminary Stellaris In-Circuit Debug Interface FTDI (ICDI) Board
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bcda", MODE="664", GROUP="plugdev"
# egnite Turtelizer 2
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bdc8", MODE="664", GROUP="plugdev"
# Section5 ICEbear
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="c140", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="c141", MODE="664", GROUP="plugdev"
# Amontec JTAGkey and JTAGkey-tiny
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="cff8", MODE="664", GROUP="plugdev"
# TI ICDI
ATTRS{idVendor}=="0451", ATTRS{idProduct}=="c32a", MODE="664", GROUP="plugdev"
# STLink v1
ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3744", MODE="664", GROUP="plugdev"
# STLink v2
ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3748", MODE="664", GROUP="plugdev"
# STLink v2-1
ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", MODE="664", GROUP="plugdev"
# Hilscher NXHX Boards
ATTRS{idVendor}=="0640", ATTRS{idProduct}=="0028", MODE="664", GROUP="plugdev"
# Hitex STR9-comStick
ATTRS{idVendor}=="0640", ATTRS{idProduct}=="002c", MODE="664", GROUP="plugdev"
# Hitex STM32-PerformanceStick
ATTRS{idVendor}=="0640", ATTRS{idProduct}=="002d", MODE="664", GROUP="plugdev"
# Altera USB Blaster
ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6001", MODE="664", GROUP="plugdev"
# Amontec JTAGkey-HiSpeed
ATTRS{idVendor}=="0fbb", ATTRS{idProduct}=="1000", MODE="664", GROUP="plugdev"
# SEGGER J-Link
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0101", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0102", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0103", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0104", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0105", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0107", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0108", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1010", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1011", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1012", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1013", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1014", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1015", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1016", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1017", MODE="664", GROUP="plugdev"
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1018", MODE="664", GROUP="plugdev"
# Raisonance RLink
ATTRS{idVendor}=="138e", ATTRS{idProduct}=="9000", MODE="664", GROUP="plugdev"
# Debug Board for Neo1973
ATTRS{idVendor}=="1457", ATTRS{idProduct}=="5118", MODE="664", GROUP="plugdev"
# Olimex ARM-USB-OCD
ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="0003", MODE="664", GROUP="plugdev"
# Olimex ARM-USB-OCD-TINY
ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="0004", MODE="664", GROUP="plugdev"
# Olimex ARM-JTAG-EW
ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="001e", MODE="664", GROUP="plugdev"
# Olimex ARM-USB-OCD-TINY-H
ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="002a", MODE="664", GROUP="plugdev"
# Olimex ARM-USB-OCD-H
ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="002b", MODE="664", GROUP="plugdev"
# USBprog with OpenOCD firmware
ATTRS{idVendor}=="1781", ATTRS{idProduct}=="0c63", MODE="664", GROUP="plugdev"
# TI/Luminary Stellaris In-Circuit Debug Interface (ICDI) Board
ATTRS{idVendor}=="1cbe", ATTRS{idProduct}=="00fd", MODE="664", GROUP="plugdev"
# Marvell Sheevaplug
ATTRS{idVendor}=="9e88", ATTRS{idProduct}=="9e8f", MODE="664", GROUP="plugdev"
# Keil Software, Inc. ULink
ATTRS{idVendor}=="c251", ATTRS{idProduct}=="2710", MODE="664", GROUP="plugdev"
# CMSIS-DAP compatible adapters
ATTRS{product}=="*CMSIS-DAP*", MODE="664", GROUP="plugdev"
LABEL="openocd_rules_end"

68
contrib/coresight-trace.txt
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@ -1,68 +0,0 @@
+OpenOCD and CoreSight Tracing
+
Many recent ARM chips (Using e..g. Cortex-M3 and
Cortex-M4 cores) support CoreSight debug/trace.
This note sketches an approach currently planned for those cores
with OpenOCD.
This tracing data can help debug and tune ARM software, but not
all cores support tracing. Some support more extensive tracing
other cores with trace support +should be able to use the same
approach and maybe some of the same analysis code.
+the Cortex-M3 is assumed here to be the
+core in use, for simplicity and to reflect current OpenOCD users.
This note summarizes a software model to generate, collect, and
analyze such trace data . That is not fully implemented as of early
January 2011, +and thus is not *yet* usable.
+
+
+Some microcontroller cores support a low pin-count Single-wire trace,
with a mode where +trace data is emitted (usually to a UART. To use
this mode, +SWD must be in use.
+At this writing, OpenOCD SWD support is not yet complete either.
(There are also multi-wire trace ports requiring more complex debug
adapters than OpenOCD currently supports, and offering richer data.
+
+
+* ENABLING involves activating SWD and (single wire) trace.
+
+current expectations are that OpenOCD itself will handle enabling;
activating single wire trace involves a debug adapter interaction, and
collecting that trace data requires particular (re)wiring.
+
+* CONFIGURATION involves setting up ITM and/or ETM modules to emit the
+desired data from the Cortex core. (This might include dumping
+event counters printf-style messages; code profiling; and more. Not all
+cores offer the same trace capabilities.
+
+current expectations are that Tcl scripts will be used to configure these
+modules for the desired tracing, by direct writes to registers. In some
+cases (as with RTOS event tracking and similar messaging, this might
+be augmented or replaced by user code running on the ARM core.
+
+COLLECTION involves reading that trace data, probably through UART, and
+saving it in a useful format to analyse For now, deferred analysis modes
are assumed, not than real-time or interactive ones.
+
+
+current expectations are to to dump data in text using contrib/itmdump.c
+or derived tools, and to post-process it into reports. Such reports might
+include program messaging (such as application data streams via ITM, maybe
+using printf type messaging; code coverage analysis or so forth. Recent
+versions of CMSIS software reserve some ITM codespace for RTOS event
tracing and include ITM messaging support.
Clearly some of that data would be valuable for interactive debugging.
+
+Should someone get ambitious, GUI reports should be possible. GNU tools
+for simpler reports like gprof may be simpler to support at first.
+In any case, OpenOCD is not currently GUI-oriented. Accordingly, we now
+expect any such graphics to come from postprocessing.
measurments for RTOS event timings should also be easy to collect.
+Examples include context and message switch times, as well as times
for application interactions.
+

119
contrib/cross-build.sh
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@ -1,119 +0,0 @@
#!/bin/sh
# This is an example of how to do a cross-build of OpenOCD using pkg-config.
# Cross-building with pkg-config is deceptively hard and most guides and
# tutorials are incomplete or give bad advice. Some of the traps that are easy
# to fall in but handled by this script are:
#
# * Polluting search paths and flags with values from the build system.
# * Faulty pkg-config wrappers shipped with distribution packaged cross-
# toolchains.
# * Build failing because pkg-config discards some paths even though they are
# correctly listed in the .pc file.
# * Getting successfully built binaries that cannot find runtime data because
# paths refer to the build file system.
#
# This script is probably more useful as a reference than as a complete build
# tool but for some configurations it may be usable as-is. It only cross-
# builds libusb-1.0 from source, but the script can be extended to build other
# prerequisities in a similar manner.
#
# Usage:
# export LIBUSB1_SRC=/path/to/libusb-1.0
# export HIDAPI_SRC=/path/to/hidapi
# export OPENOCD_CONFIG="--enable-..."
# cd /work/dir
# /path/to/openocd/contrib/cross-build.sh <host-triplet>
#
# For static linking, a workaround is to
# export LIBUSB1_CONFIG="--enable-static --disable-shared"
#
# All the paths must not contain any spaces.
set -e -x
WORK_DIR=$PWD
## Source code paths, customize as necessary
: ${OPENOCD_SRC:="`dirname "$0"`/.."}
: ${LIBUSB1_SRC:=/path/to/libusb}
: ${HIDAPI_SRC:=/path/to/hidapi}
OPENOCD_SRC=`readlink -m $OPENOCD_SRC`
LIBUSB1_SRC=`readlink -m $LIBUSB1_SRC`
HIDAPI_SRC=`readlink -m $HIDAPI_SRC`
HOST_TRIPLET=$1
BUILD_DIR=$WORK_DIR/$HOST_TRIPLET-build
LIBUSB1_BUILD_DIR=$BUILD_DIR/libusb1
HIDAPI_BUILD_DIR=$BUILD_DIR/hidapi
OPENOCD_BUILD_DIR=$BUILD_DIR/openocd
## Root of host file tree
SYSROOT=$WORK_DIR/$HOST_TRIPLET-root
## Install location within host file tree
: ${PREFIX=/usr}
## OpenOCD-only install dir for packaging
PACKAGE_DIR=$WORK_DIR/openocd_`git --git-dir=$OPENOCD_SRC/.git describe`_$HOST_TRIPLET
#######
# Create pkg-config wrapper and make sure it's used
export PKG_CONFIG=$WORK_DIR/$HOST_TRIPLET-pkg-config
cat > $PKG_CONFIG <<EOF
#!/bin/sh
SYSROOT=$SYSROOT
export PKG_CONFIG_DIR=
export PKG_CONFIG_LIBDIR=\${SYSROOT}$PREFIX/lib/pkgconfig:\${SYSROOT}$PREFIX/share/pkgconfig
export PKG_CONFIG_SYSROOT_DIR=\${SYSROOT}
# The following have to be set to avoid pkg-config to strip /usr/include and /usr/lib from paths
# before they are prepended with the sysroot path. Feels like a pkg-config bug.
export PKG_CONFIG_ALLOW_SYSTEM_CFLAGS=
export PKG_CONFIG_ALLOW_SYSTEM_LIBS=
exec pkg-config "\$@"
EOF
chmod +x $PKG_CONFIG
# Clear out work dir
rm -rf $SYSROOT $BUILD_DIR
mkdir -p $SYSROOT
# libusb-1.0 build & install into sysroot
mkdir -p $LIBUSB1_BUILD_DIR
cd $LIBUSB1_BUILD_DIR
$LIBUSB1_SRC/configure --build=`$LIBUSB1_SRC/config.guess` --host=$HOST_TRIPLET \
--with-sysroot=$SYSROOT --prefix=$PREFIX \
$LIBUSB1_CONFIG
make
make install DESTDIR=$SYSROOT
# hidapi build & install into sysroot
if [ -d $HIDAPI_SRC ] ; then
mkdir -p $HIDAPI_BUILD_DIR
cd $HIDAPI_BUILD_DIR
$HIDAPI_SRC/configure --build=`$HIDAPI_SRC/config.guess` --host=$HOST_TRIPLET \
--with-sysroot=$SYSROOT --prefix=$PREFIX \
$HIDAPI_CONFIG
make
make install DESTDIR=$SYSROOT
fi
# OpenOCD build & install into sysroot
mkdir -p $OPENOCD_BUILD_DIR
cd $OPENOCD_BUILD_DIR
$OPENOCD_SRC/configure --build=`$OPENOCD_SRC/config.guess` --host=$HOST_TRIPLET \
--with-sysroot=$SYSROOT --prefix=$PREFIX \
$OPENOCD_CONFIG
make
make install DESTDIR=$SYSROOT
# Separate OpenOCD install w/o dependencies. OpenOCD will have to be linked
# statically or have dependencies packaged/installed separately.
make install DESTDIR=$PACKAGE_DIR

124
contrib/gen-stellaris-part-header.pl
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@ -1,124 +0,0 @@
#!/usr/bin/perl
# Automatically generates the StellarisParts struct in src/flash/nor/stellaris.c
# Uses the header files from TI/Luminary's StellarisWare complete Firmware Development Package
# available from: http://www.luminarymicro.com/products/software_updates.html
$comment = "// Autogenerated by contrib/gen-stellaris-part-header.pl
// From Stellaris Firmware Development Package revision";
$struct_header = "static const struct {
uint8_t class;
uint8_t partno;
const char *partname;
} StellarisParts[] = {
";
$struct_footer = "\t{0xFF, 0x00, \"Unknown Part\"}\n};\n";
$#ARGV == 1 || die "Usage: $0 <inc directory> <output file>\n";
-d $ARGV[0] || die $ARGV[0]." is not a directory\n";
$dir = $ARGV[0];
-f $ARGV[1] || die $ARGV[1]." is not a file\n";
$file = $ARGV[1];
print STDERR "Scanning $dir, Updating $file\n";
opendir(DIR, $dir) || die "can't open $dir: $!";
@files = readdir(DIR);
closedir(DIR);
@header_files = sort(grep(/lm.+\.h/, @files));
$ver = 0;
$new_struct = $struct_header;
process_file(@header_files);
$new_struct .= $struct_footer;
$dump = "$comment $ver\n$new_struct";
{
local($/, *INPUT);
open(INPUT, $file) || die "can't open $file: $!";
$contents = <INPUT>;
close(INPUT);
}
$old_struct = qr/((^\/\/.*?\n)*)\Q$struct_header\E.*?$struct_footer/sm;
$contents =~ s/$old_struct/$dump/;
open(OUTPUT, ">$file") || die "can't open file $file for writing: $!";
print OUTPUT $contents;
close(OUTPUT);
sub process_file {
foreach $h_file (@_) {
($base) = ($h_file =~ m/lm..(.{3,7})\.h/ig);
$base = uc($base);
local($/, *FILE);
open(FILE, "$dir/$h_file");
$content = <FILE>;
close(FILE);
$invalid = 0;
if ($content =~ /This is part of revision (\d+) of/) {
if ($ver != 0 and $ver != $1) {
print STDERR "File version mismatch: $ver != $1\n";
$ver = max($ver, $1);
} else {
$ver = $1;
}
}
if ($content =~ /SYSCTL_DID0_CLASS_[^M].+?0x(\S+)/s) {
$class = hex($1) >> 16;
} else {
# attempt another way to get class
if ($content =~ /\s(\S+)-class/) {
$class = getclass($1);
if ($class eq 0xFF) {
print STDERR "$h_file unknown class\n";
$invalid = 1;
}
} else {
print STDERR "$h_file is missing SYSCTL_DID0_CLASS_\n";
$class = 0;
$invalid = 1;
}
}
if ($content =~ /SYSCTL_DID1_PRTNO_$base.+0x(\S+)/) {
$prtno = hex($1);
$base = "LM3S" . $base;
} else {
# LM4F have a changed header
if ($content =~ /SYSCTL_DID1_PRTNO_LM4F$base.+?0x(\S+)/s) {
$prtno = hex($1);
$base = "LM4F" . $base;
} else {
print STDERR "$h_file is missing SYSCTL_DID1_PRTNO\n";
$prtno = 0;
$invalid = 1;
}
}
$new_member = sprintf "{0x%02X, 0x%02X, \"%s\"},", $class, $prtno >> 16, $base;
if ($invalid == 1) {
#$new_struct .= "\t//$new_member\t// Invalid\n";
} else {
$new_struct .= "\t$new_member\n";
}
}
}
sub getclass {
$class = $_[0];
if ($class =~ /Sandstorm/i) {
return 0;
} elsif ($class =~ /Fury/i) {
return 1;
} elsif ($class =~ /DustDevil/i) {
return 3;
} elsif ($class =~ /Tempest/i) {
return 4;
} elsif ($class =~ /Blizzard/i) {
return 5;
} elsif ($class =~ /Firestorm/i) {
return 6;
}
return 0xFF;
}

459
contrib/itmdump.c
View File

@ -1,459 +0,0 @@
/*
* Copyright (C) 2010 by David Brownell
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or (at
* your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Simple utility to parse and dump ARM Cortex-M3 SWO trace output. Once the
* mechanisms work right, this information can be used for various purposes
* including profiling (particularly easy for flat PC-sample profiles) and
* for debugging.
*
* SWO is the Single Wire Output found on some ARM cores, most notably on the
* Cortex-M3. It combines data from several sources:
*
* - Software trace (ITM): so-called "printf-style" application messaging
* using "ITM stimulus ports"; and differential timestamps.
* - Hardware trace (DWT): for profiling counters and comparator matches.
* - TPIU may issue sync packets.
*
* The trace data format is defined in Appendix E, "Debug ITM and DWT packet
* protocol", of the ARMv7-M Architecture Reference Manual (DDI 0403C). It
* is a superset of the ITM data format from the Coresight TRM.
*
* The trace data has two encodings. The working assumption is that data
* gets into this program using the UART encoding.
*/
#include <errno.h>
#include <libgen.h>
#include <stdio.h>
#include <stdbool.h>
#include <string.h>
#include <unistd.h>
unsigned int dump_swit;
/* Example ITM trace word (0xWWXXYYZZ) parsing for task events, sent
* on port 31 (Reserved for "the" RTOS in CMSIS v1.30)
* WWXX: event code (0..3 pre-assigned, 4..15 reserved)
* YY: task priority
* ZZ: task number
*
* NOTE that this specific encoding could be space-optimized; and that
* trace data streams could also be history-sensitive.
*/
static void show_task(int port, unsigned data)
{
unsigned code = data >> 16;
char buf[16];
if (dump_swit)
return;
switch (code) {
case 0:
strcpy(buf, "run");
break;
case 1:
strcpy(buf, "block");
break;
case 2:
strcpy(buf, "create");
break;
case 3:
strcpy(buf, "destroy");
break;
/* 4..15 reserved for other infrastructure ops */
default:
sprintf(buf, "code %d", code);
break;
}
printf("TASK %d, pri %d: %s",
(data >> 0) & 0xff,
(data >> 8) & 0xff,
buf);
}
static void show_reserved(FILE *f, char *label, int c)
{
unsigned i;
if (dump_swit)
return;
printf("%s - %#02x", label, c);
for (i = 0; (c & 0x80) && i < 4; i++) {
c = fgetc(f);
if (c == EOF) {
printf("(ERROR %d - %s) ", errno, strerror(errno));
break;
}
printf(" %#02x", c);
}
printf("\n");
}
static bool read_varlen(FILE *f, int c, unsigned *value)
{
unsigned size;
unsigned char buf[4];
*value = 0;
switch (c & 3) {
case 3:
size = 4;
break;
case 2:
size = 2;
break;
case 1:
size = 1;
break;
default:
printf("INVALID SIZE\n");
return false;
}
memset(buf, 0, sizeof buf);
if (fread(buf, 1, size, f) != size)
goto err;
*value = (buf[3] << 24)
+ (buf[2] << 16)
+ (buf[1] << 8)
+ (buf[0] << 0);
return true;
err:
printf("(ERROR %d - %s)\n", errno, strerror(errno));
return false;
}
static void show_hard(FILE *f, int c)
{
unsigned type = c >> 3;
unsigned value;
char *label;
if (dump_swit)
return;
printf("DWT - ");
if (!read_varlen(f, c, &value))
return;
printf("%#x", value);
switch (type) {
case 0: /* event counter wrapping */
printf("overflow %s%s%s%s%s%s",
(value & (1 << 5)) ? "cyc " : "",
(value & (1 << 4)) ? "fold " : "",
(value & (1 << 3)) ? "lsu " : "",
(value & (1 << 2)) ? "slp " : "",
(value & (1 << 1)) ? "exc " : "",
(value & (1 << 0)) ? "cpi " : "");
break;
case 1: /* exception tracing */
switch (value >> 12) {
case 1:
label = "entry to";
break;
case 2:
label = "exit from";
break;
case 3:
label = "return to";
break;
default:
label = "?";
break;
}
printf("%s exception %d", label, value & 0x1ff);
break;
case 2: /* PC sampling */
if (c == 0x15)
printf("PC - sleep");
else
printf("PC - %#08x", value);
break;
case 8: /* data tracing, pc value */
case 10:
case 12:
case 14:
printf("Data trace %d, PC %#08x", (c >> 4) & 3, value);
/* optionally followed by data value */
break;
case 9: /* data tracing, address offset */
case 11:
case 13:
case 15:
printf("Data trace %d, address offset %#04x",
(c >> 4) & 3, value);
/* always followed by data value */
break;
case 16 ... 23: /* data tracing, data value */
printf("Data trace %d, ", (c >> 4) & 3);
label = (c & 0x8) ? "write" : "read";
switch (c & 3) {
case 3:
printf("word %s, value %#08x", label, value);
break;
case 2:
printf("halfword %s, value %#04x", label, value);
break;
case 1:
printf("byte %s, value %#02x", label, value);
break;
}
break;
default:
printf("UNDEFINED, rawtype: %x", type);
break;
}
printf("\n");
return;
}
/*
* Table of SWIT (SoftWare InstrumentTation) message dump formats, for
* ITM port 0..31 application data.
*
* Eventually this should be customizable; all usage is application defined.
*
* REVISIT there can be up to 256 trace ports, via "ITM Extension" packets
*/
struct {
int port;
void (*show)(int port, unsigned data);
} format[] = {
{ .port = 31, .show = show_task, },
};
static void show_swit(FILE *f, int c)
{
unsigned port = c >> 3;
unsigned value = 0;
unsigned i;
if (port + 1 == dump_swit) {
if (!read_varlen(f, c, &value))
return;
printf("%c", value);
return;
}
if (!read_varlen(f, c, &value))
return;
if (dump_swit)
return;
printf("SWIT %u - ", port);
printf("%#08x", value);
for (i = 0; i < sizeof(format) / sizeof(format[0]); i++) {
if (format[i].port == port) {
printf(", ");
format[i].show(port, value);
break;
}
}
printf("\n");
return;
}
static void show_timestamp(FILE *f, int c)
{
unsigned counter = 0;
char *label = "";
bool delayed = false;
if (dump_swit)
return;
printf("TIMESTAMP - ");
/* Format 2: header only */
if (!(c & 0x80)) {
switch (c) {
case 0: /* sync packet -- coding error! */
case 0x70: /* overflow -- ditto! */
printf("ERROR - %#02x\n", c);
break;
default:
/* synchronous to ITM */
counter = c >> 4;
goto done;
}
return;
}
/* Format 1: one to four bytes of data too */
switch (c >> 4) {
default:
label = ", reserved control\n";
break;
case 0xc:
/* synchronous to ITM */
break;
case 0xd:
label = ", timestamp delayed";
delayed = true;
break;
case 0xe:
label = ", packet delayed";
delayed = true;
break;
case 0xf:
label = ", packet and timetamp delayed";
delayed = true;
break;
}
c = fgetc(f);
if (c == EOF)
goto err;
counter = c & 0x7f;
if (!(c & 0x80))
goto done;
c = fgetc(f);
if (c == EOF)
goto err;
counter |= (c & 0x7f) << 7;
if (!(c & 0x80))
goto done;
c = fgetc(f);
if (c == EOF)
goto err;
counter |= (c & 0x7f) << 14;
if (!(c & 0x80))
goto done;
c = fgetc(f);
if (c == EOF)
goto err;
counter |= (c & 0x7f) << 21;
done:
/* REVISIT should we try to convert from delta values? */
printf("+%u%s\n", counter, label);
return;
err:
printf("(ERROR %d - %s) ", errno, strerror(errno));
goto done;
}
int main(int argc, char **argv)
{
FILE *f = stdin;
int c;
/* parse arguments */
while ((c = getopt(argc, argv, "f:d:")) != EOF) {
switch (c) {
case 'f':
/* e.g. from UART connected to /dev/ttyUSB0 */
f = fopen(optarg, "r");
if (!f) {
perror(optarg);
return 1;
}
break;
case 'd':
dump_swit = atoi(optarg);
break;
default:
fprintf(stderr, "usage: %s [-f input]",
basename(argv[0]));
return 1;
}
}
/* Parse data ... records have a header then data bytes.
* NOTE: we assume getc() deals in 8-bit bytes.
*/
bool overflow = false;
while ((c = getc(f)) != EOF) {
/* Sync packet ... 7 zeroes, 0x80 */
if (c == 0) {
int i;
for (i = 0; i < 6; i++) {
c = fgetc(f);
if (c == EOF)
break;
if (c != 0)
goto bad_sync;
}
c = fgetc(f);
if (c == 0x80) {
printf("SYNC\n");
continue;
}
bad_sync:
printf("BAD SYNC\n");
continue;
}
/* Overflow packet */
if (c == 0x70) {
/* REVISIT later, report just what overflowed!
* Timestamp and SWIT can happen. Non-ITM too?
*/
overflow = true;
printf("OVERFLOW ...\n");
continue;
}
overflow = false;
switch (c & 0x0f) {
case 0x00: /* Timestamp */
show_timestamp(f, c);
break;
case 0x04: /* "Reserved" */
show_reserved(f, "RESERVED", c);
break;
case 0x08: /* ITM Extension */
/* FIXME someday, handle these ... */
show_reserved(f, "ITM EXT", c);
break;
case 0x0c: /* DWT Extension */
show_reserved(f, "DWT EXT", c);
break;
default:
if (c & 4)
show_hard(f, c);
else
show_swit(f, c);
break;
}
}
return 0;
}

19
contrib/libdcc/README
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@ -1,19 +0,0 @@
This code is an example of using the openocd debug message system.
Before the message output is seen in the debug window, the functionality
will need enabling:
From the gdb prompt:
monitor target_request debugmsgs enable
monitor trace point 1
From the Telnet prompt:
target_request debugmsgs enable
trace point 1
To see how many times the trace point was hit:
(monitor) trace point 1
Spen
spen@spen-soft.co.uk

157
contrib/libdcc/dcc_stdio.c
View File

@ -1,157 +0,0 @@
/***************************************************************************
* Copyright (C) 2008 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* Copyright (C) 2008 by Frederik Kriewtz *
* frederik@kriewitz.eu *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#include "dcc_stdio.h"
#define TARGET_REQ_TRACEMSG 0x00
#define TARGET_REQ_DEBUGMSG_ASCII 0x01
#define TARGET_REQ_DEBUGMSG_HEXMSG(size) (0x01 | ((size & 0xff) << 8))
#define TARGET_REQ_DEBUGCHAR 0x02
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_6SM__)
/* we use the System Control Block DCRDR reg to simulate a arm7_9 dcc channel
* DCRDR[7:0] is used by target for status
* DCRDR[15:8] is used by target for write buffer
* DCRDR[23:16] is used for by host for status
* DCRDR[31:24] is used for by host for write buffer */
#define NVIC_DBG_DATA_R (*((volatile unsigned short *)0xE000EDF8))
#define BUSY 1
void dbg_write(unsigned long dcc_data)
{
int len = 4;
while (len--)
{
/* wait for data ready */
while (NVIC_DBG_DATA_R & BUSY);
/* write our data and set write flag - tell host there is data*/
NVIC_DBG_DATA_R = (unsigned short)(((dcc_data & 0xff) << 8) | BUSY);
dcc_data >>= 8;
}
}
#elif defined(__ARM_ARCH_4T__) || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5T__)
void dbg_write(unsigned long dcc_data)
{
unsigned long dcc_status;
do {
asm volatile("mrc p14, 0, %0, c0, c0" : "=r" (dcc_status));
} while (dcc_status & 0x2);
asm volatile("mcr p14, 0, %0, c1, c0" : : "r" (dcc_data));
}
#else
#error unsupported target
#endif
void dbg_trace_point(unsigned long number)
{
dbg_write(TARGET_REQ_TRACEMSG | (number << 8));
}
void dbg_write_u32(const unsigned long *val, long len)
{
dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(4) | ((len & 0xffff) << 16));
while (len > 0)
{
dbg_write(*val);
val++;
len--;
}
}
void dbg_write_u16(const unsigned short *val, long len)
{
unsigned long dcc_data;
dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(2) | ((len & 0xffff) << 16));
while (len > 0)
{
dcc_data = val[0]
| ((len > 1) ? val[1] << 16: 0x0000);
dbg_write(dcc_data);
val += 2;
len -= 2;
}
}
void dbg_write_u8(const unsigned char *val, long len)
{
unsigned long dcc_data;
dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(1) | ((len & 0xffff) << 16));
while (len > 0)
{
dcc_data = val[0]
| ((len > 1) ? val[1] << 8 : 0x00)
| ((len > 2) ? val[2] << 16 : 0x00)
| ((len > 3) ? val[3] << 24 : 0x00);
dbg_write(dcc_data);
val += 4;
len -= 4;
}
}
void dbg_write_str(const char *msg)
{
long len;
unsigned long dcc_data;
for (len = 0; msg[len] && (len < 65536); len++);
dbg_write(TARGET_REQ_DEBUGMSG_ASCII | ((len & 0xffff) << 16));
while (len > 0)
{
dcc_data = msg[0]
| ((len > 1) ? msg[1] << 8 : 0x00)
| ((len > 2) ? msg[2] << 16 : 0x00)
| ((len > 3) ? msg[3] << 24 : 0x00);
dbg_write(dcc_data);
msg += 4;
len -= 4;
}
}
void dbg_write_char(char msg)
{
dbg_write(TARGET_REQ_DEBUGCHAR | ((msg & 0xff) << 16));
}

35
contrib/libdcc/dcc_stdio.h
View File

@ -1,35 +0,0 @@
/***************************************************************************
* Copyright (C) 2008 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#ifndef DCC_STDIO_H
#define DCC_STDIO_H
void dbg_trace_point(unsigned long number);
void dbg_write_u32(const unsigned long *val, long len);
void dbg_write_u16(const unsigned short *val, long len);
void dbg_write_u8(const unsigned char *val, long len);
void dbg_write_str(const char *msg);
void dbg_write_char(char msg);
#endif /* DCC_STDIO_H */

58
contrib/libdcc/example.c
View File

@ -1,58 +0,0 @@
/***************************************************************************
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* Copyright (C) 2008 by Frederik Kriewtz *
* frederik@kriewitz.eu *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#include "dcc_stdio.h"
/* enable openocd debugmsg at the gdb prompt:
* monitor target_request debugmsgs enable
*
* create a trace point:
* monitor trace point 1
*
* to show how often the trace point was hit:
* monitor trace point
*/
int main(void)
{
dbg_write_str("hello world");
dbg_write_char('t');
dbg_write_char('e');
dbg_write_char('s');
dbg_write_char('t');
dbg_write_char('\n');
unsigned long test_u32 = 0x01234567;
dbg_write_u32(&test_u32, 1);
static const unsigned short test_u16[] = {0x0123, 0x4567, 0x89AB, 0xCDEF, 0x0123, 0x4567, 0x89AB, 0xCDEF};
dbg_write_u16(test_u16, 8);
static const unsigned char test_u8[] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0XDD, 0xEE, 0xFF};
dbg_write_u8(test_u8, 16);
while(1)
{
dbg_trace_point(0);
}
}

33
contrib/loaders/Makefile
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@ -1,33 +0,0 @@
.PHONY: arm clean-arm
all: arm
common_dirs = \
checksum \
erase_check \
watchdog
ARM_CROSS_COMPILE ?= arm-none-eabi-
arm_dirs = \
flash/fm4 \
flash/kinetis_ke \
flash/xmc1xxx
arm:
for d in $(common_dirs); do \
$(MAKE) -C $$d arm; \
done
for d in $(arm_dirs); do \
$(MAKE) -C $$d all CROSS_COMPILE=$(ARM_CROSS_COMPILE); \
done
clean-arm:
for d in $(arm_dirs); do \
$(MAKE) -C $$d clean; \
done
clean: clean-arm
for d in $(common_dirs); do \
$(MAKE) -C $$d clean; \
done

33
contrib/loaders/README
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@ -1,33 +0,0 @@
Included in these directories are the src to the various ram loaders used
within openocd.
** target checksum loaders **
checksum/armv4_5_crc.s :
- ARMv4 and ARMv5 checksum loader : see target/arm_crc_code.c:arm_crc_code
checksum/armv7m_crc.s :
- ARMv7m checksum loader : see target/armv7m.c:cortex_m_crc_code
checksum/mips32.s :
- MIPS32 checksum loader : see target/mips32.c:mips_crc_code
** target flash loaders **
flash/pic32mx.s :
- Microchip PIC32 flash loader : see flash/nor/pic32mx.c:pic32mx_flash_write_code
flash/stellaris.s :
- TI Stellaris flash loader : see flash/nor/stellaris.c:stellaris_write_code
flash/stm32x.s :
- ST STM32 flash loader : see flash/nor/stm32x.c:stm32x_flash_write_code
flash/str7x.s :
- ST STR7 flash loader : see flash/nor/str7x.c:str7x_flash_write_code
flash/str9x.s :
- ST STR9 flash loader : see flash/nor/str9x.c:str9x_flash_write_code
Spencer Oliver
spen@spen-soft.co.uk

30
contrib/loaders/checksum/Makefile
View File

@ -1,30 +0,0 @@
BIN2C = ../../../src/helper/bin2char.sh
ARM_CROSS_COMPILE ?= arm-none-eabi-
ARM_AS ?= $(ARM_CROSS_COMPILE)as
ARM_OBJCOPY ?= $(ARM_CROSS_COMPILE)objcopy
ARM_AFLAGS = -EL
arm: armv4_5_crc.inc armv7m_crc.inc
armv4_5_%.elf: armv4_5_%.s
$(ARM_AS) $(ARM_AFLAGS) $< -o $@
armv4_5_%.bin: armv4_5_%.elf
$(ARM_OBJCOPY) -Obinary $< $@
armv4_5_%.inc: armv4_5_%.bin
$(BIN2C) < $< > $@
armv7m_%.elf: armv7m_%.s
$(ARM_AS) $(ARM_AFLAGS) $< -o $@
armv7m_%.bin: armv7m_%.elf
$(ARM_OBJCOPY) -Obinary $< $@
armv7m_%.inc: armv7m_%.bin
$(BIN2C) < $< > $@
clean:
-rm -f *.elf *.bin *.inc

7
contrib/loaders/checksum/armv4_5_crc.inc
View File

@ -1,7 +0,0 @@
/* Autogenerated with ../../../src/helper/bin2char.sh */
0x00,0x20,0xa0,0xe1,0x00,0x00,0xe0,0xe3,0x01,0x30,0xa0,0xe1,0x00,0x40,0xa0,0xe3,
0x0b,0x00,0x00,0xea,0x04,0x10,0xd2,0xe7,0x30,0x70,0x9f,0xe5,0x01,0x0c,0x20,0xe0,
0x00,0x50,0xa0,0xe3,0x00,0x00,0x50,0xe3,0x80,0x60,0xa0,0xe1,0x01,0x50,0x85,0xe2,
0x06,0x00,0xa0,0xe1,0x07,0x00,0x26,0xb0,0x08,0x00,0x55,0xe3,0xf8,0xff,0xff,0x1a,
0x01,0x40,0x84,0xe2,0x03,0x00,0x54,0xe1,0xf1,0xff,0xff,0x1a,0x70,0x00,0x20,0xe1,
0xb7,0x1d,0xc1,0x04,

58
contrib/loaders/checksum/armv4_5_crc.s
View File

@ -1,58 +0,0 @@
/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
r0 - address in - crc out
r1 - char count
*/
.text
.arm
_start:
main:
mov r2, r0
mov r0, #0xffffffff /* crc */
mov r3, r1
mov r4, #0
b ncomp
nbyte:
ldrb r1, [r2, r4]
ldr r7, CRC32XOR
eor r0, r0, r1, asl #24
mov r5, #0
loop:
cmp r0, #0
mov r6, r0, asl #1
add r5, r5, #1
mov r0, r6
eorlt r0, r6, r7
cmp r5, #8
bne loop
add r4, r4, #1
ncomp:
cmp r4, r3
bne nbyte
end:
bkpt #0
CRC32XOR: .word 0x04c11db7
.end

5
contrib/loaders/checksum/armv7m_crc.inc
View File

@ -1,5 +0,0 @@
/* Autogenerated with ../../../src/helper/bin2char.sh */
0x02,0x46,0x00,0x20,0xc0,0x43,0x0a,0x4e,0x0b,0x46,0x00,0x24,0x0d,0xe0,0x11,0x5d,
0x09,0x06,0x48,0x40,0x00,0x25,0x00,0x28,0x02,0xda,0x40,0x00,0x70,0x40,0x00,0xe0,
0x40,0x00,0x01,0x35,0x08,0x2d,0xf6,0xd1,0x01,0x34,0x9c,0x42,0xef,0xd1,0x00,0xbe,
0xb7,0x1d,0xc1,0x04,

71
contrib/loaders/checksum/armv7m_crc.s
View File

@ -1,71 +0,0 @@
/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
parameters:
r0 - address in - crc out
r1 - char count
*/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.align 2
_start:
main:
mov r2, r0
movs r0, #0
mvns r0, r0
ldr r6, CRC32XOR
mov r3, r1
movs r4, #0
b ncomp
nbyte:
ldrb r1, [r2, r4]
lsls r1, r1, #24
eors r0, r0, r1
movs r5, #0
loop:
cmp r0, #0
bge notset
lsls r0, r0, #1
eors r0, r0, r6
b cont
notset:
lsls r0, r0, #1
cont:
adds r5, r5, #1
cmp r5, #8
bne loop
adds r4, r4, #1
ncomp:
cmp r4, r3
bne nbyte
bkpt #0
.align 2
CRC32XOR: .word 0x04c11db7
.end

72
contrib/loaders/checksum/mips32.s
View File

@ -1,72 +0,0 @@
/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.global main
.text
.set noreorder
/* params:
* $a0 address in
* $a1 byte count
* vars
* $a0 crc
* $a1 crc data byte
* temps:
* t3 v0 a3 a2 t0 v1
*/
.ent main
main:
addiu $t4, $a0, 0 /* address in */
addiu $t2, $a1, 0 /* count */
addiu $a0, $zero, 0xffffffff /* a0 crc - result */
beq $zero, $zero, ncomp
addiu $t3, $zero, 0 /* clear bytes read */
nbyte:
lb $a1, ($t4) /* load byte from source address */
addi $t4, $t4, 1 /* inc byte count */
crc:
sll $a1, $a1, 24
lui $v0, 0x04c1
xor $a0, $a0, $a1
ori $a3, $v0, 0x1db7
addu $a2, $zero, $zero /* clear bit count */
loop:
sll $t0, $a0, 1
addiu $a2, $a2, 1 /* inc bit count */
slti $a0, $a0, 0
xor $t1, $t0, $a3
movn $t0, $t1, $a0
slti $v1, $a2, 8 /* 8bits processed */
bne $v1, $zero, loop
addu $a0, $t0, $zero
ncomp:
bne $t2, $t3, nbyte /* all bytes processed */
addiu $t3, $t3, 1
wait:
sdbbp
.end main

30
contrib/loaders/erase_check/Makefile
View File

@ -1,30 +0,0 @@
BIN2C = ../../../src/helper/bin2char.sh
ARM_CROSS_COMPILE ?= arm-none-eabi-
ARM_AS ?= $(ARM_CROSS_COMPILE)as
ARM_OBJCOPY ?= $(ARM_CROSS_COMPILE)objcopy
ARM_AFLAGS = -EL
arm: armv4_5_erase_check.inc armv7m_erase_check.inc armv7m_0_erase_check.inc
armv4_5_%.elf: armv4_5_%.s
$(ARM_AS) $(ARM_AFLAGS) $< -o $@
armv4_5_%.bin: armv4_5_%.elf
$(ARM_OBJCOPY) -Obinary $< $@
armv4_5_%.inc: armv4_5_%.bin
$(BIN2C) < $< > $@
armv7m_%.elf: armv7m_%.s
$(ARM_AS) $(ARM_AFLAGS) $< -o $@
armv7m_%.bin: armv7m_%.elf
$(ARM_OBJCOPY) -Obinary $< $@
armv7m_%.inc: armv7m_%.bin
$(BIN2C) < $< > $@
clean:
-rm -f *.elf *.bin *.inc

3
contrib/loaders/erase_check/armv4_5_erase_check.inc
View File

@ -1,3 +0,0 @@
/* Autogenerated with ../../../src/helper/bin2char.sh */
0x01,0x30,0xd0,0xe4,0x03,0x20,0x02,0xe0,0x01,0x10,0x51,0xe2,0xfb,0xff,0xff,0x1a,
0x70,0x00,0x20,0xe1,

39
contrib/loaders/erase_check/armv4_5_erase_check.s
View File

@ -1,39 +0,0 @@
/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
parameters:
r0 - address in
r1 - byte count
r2 - mask - result out
*/
.text
.arm
loop:
ldrb r3, [r0], #1
and r2, r2, r3
subs r1, r1, #1
bne loop
end:
bkpt #0
.end

2
contrib/loaders/erase_check/armv7m_0_erase_check.inc
View File

@ -1,2 +0,0 @@
/* Autogenerated with ../../../src/helper/bin2char.sh */
0x03,0x78,0x01,0x30,0x1a,0x43,0x01,0x39,0xfa,0xd1,0x00,0xbe,

45
contrib/loaders/erase_check/armv7m_0_erase_check.s
View File

@ -1,45 +0,0 @@
/***************************************************************************
* Copyright (C) 2014 by Jeff Ciesielski *
* jeffciesielski@gmail.com *
* *
* Based on the armv7m erase checker by: *
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
***************************************************************************/
/*
parameters:
r0 - address in
r1 - byte count
r2 - mask - result out
*/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.align 2
loop:
ldrb r3, [r0]
adds r0, #1
orrs r2, r2, r3
subs r1, r1, #1
bne loop
end:
bkpt #0
.end

2
contrib/loaders/erase_check/armv7m_erase_check.inc
View File

@ -1,2 +0,0 @@
/* Autogenerated with ../../../src/helper/bin2char.sh */
0x03,0x78,0x01,0x30,0x1a,0x40,0x01,0x39,0xfa,0xd1,0x00,0xbe,

45
contrib/loaders/erase_check/armv7m_erase_check.s
View File

@ -1,45 +0,0 @@
/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
parameters:
r0 - address in
r1 - byte count
r2 - mask - result out
*/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.align 2
loop:
ldrb r3, [r0]
adds r0, #1
ands r2, r2, r3
subs r1, r1, #1
bne loop
end:
bkpt #0
.end

57
contrib/loaders/flash/armv4_5_cfi_intel_16.s
View File

@ -1,57 +0,0 @@
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* algorithm register usage:
* r0: source address (in RAM)
* r1: target address (in Flash)
* r2: count
* r3: flash write command
* r4: status byte (returned to host)
* r5: busy test pattern
* r6: error test pattern
*/
loop:
ldrh r4, [r0], #2
strh r3, [r1]
strh r4, [r1]
busy:
ldrh r4, [r1]
and r7, r4, r5
cmp r7, r5
bne busy
tst r4, r6
bne done
subs r2, r2, #1
beq done
add r1, r1, #2
b loop
done:
b done
.end

57
contrib/loaders/flash/armv4_5_cfi_intel_32.s
View File

@ -1,57 +0,0 @@
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* algorithm register usage:
* r0: source address (in RAM)
* r1: target address (in Flash)
* r2: count
* r3: flash write command
* r4: status byte (returned to host)
* r5: busy test pattern
* r6: error test pattern
*/
loop:
ldr r4, [r0], #4
str r3, [r1]
str r4, [r1]
busy:
ldr r4, [r1]
and r7, r4, r5
cmp r7, r5
bne busy
tst r4, r6
bne done
subs r2, r2, #1
beq done
add r1, r1, #4
b loop
done:
b done
.end

57
contrib/loaders/flash/armv4_5_cfi_intel_8.s
View File

@ -1,57 +0,0 @@
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* algorithm register usage:
* r0: source address (in RAM)
* r1: target address (in Flash)
* r2: count
* r3: flash write command
* r4: status byte (returned to host)
* r5: busy test pattern
* r6: error test pattern
*/
loop:
ldrb r4, [r0], #1
strb r3, [r1]
strb r4, [r1]
busy:
ldrb r4, [r1]
and r7, r4, r5
cmp r7, r5
bne busy
tst r4, r6
bne done
subs r2, r2, #1
beq done
add r1, r1, #1
b loop
done:
b done
.end

75
contrib/loaders/flash/armv4_5_cfi_span_16.s
View File

@ -1,75 +0,0 @@
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrh r5, [r0], #2
strh r9, [r8]
strh r11, [r10]
strh r3, [r8]
strh r5, [r1]
nop
busy:
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #2 /* 0x2 */
b code
done:
b done
.end

66
contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s
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@ -1,66 +0,0 @@
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrh r5, [r0], #2
strh r9, [r8]
strh r11, [r10]
strh r3, [r8]
strh r5, [r1]
nop
busy:
ldrh r6, [r1]
eor r7, r5, r6
ands r7, #0x80
bne busy
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #2 /* 0x2 */
b code
done:
b done
.end

75
contrib/loaders/flash/armv4_5_cfi_span_32.s
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@ -1,75 +0,0 @@
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldr r5, [r0], #4
str r9, [r8]
str r11, [r10]
str r3, [r8]
str r5, [r1]
nop
busy:
ldr r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldr r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #4 /* 0x4 */
b code
done:
b done
.end

75
contrib/loaders/flash/armv4_5_cfi_span_8.s
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@ -1,75 +0,0 @@
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrb r5, [r0], #1
strb r9, [r8]
strb r11, [r10]
strb r3, [r8]
strb r5, [r1]
nop
busy:
ldrb r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldrb r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #1 /* 0x1 */
b code
done:
b done
.end

81
contrib/loaders/flash/armv7m_cfi_span_16.s
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@ -1,81 +0,0 @@
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.arch armv7-m
.thumb
.thumb_func
.align 2
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrh r5, [r0], #2
strh r9, [r8]
strh r11, [r10]
strh r3, [r8]
strh r5, [r1]
nop
busy:
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
beq success
add r1, r1, #2 /* 0x2 */
b code
success:
mov r5, #128 /* 0x80 */
b done
done:
bkpt #0
.end

72
contrib/loaders/flash/armv7m_cfi_span_16_dq7.s
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@ -1,72 +0,0 @@
/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.arch armv7-m
.thumb
.thumb_func
.align 2
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrh r5, [r0], #2
strh r9, [r8]
strh r11, [r10]
strh r3, [r8]
strh r5, [r1]
nop
busy:
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
bne busy
subs r2, r2, #1 /* 0x1 */
beq success
add r1, r1, #2 /* 0x2 */
b code
success:
mov r5, #128 /* 0x80 */
b done
done:
bkpt #0
.end

60
contrib/loaders/flash/armv7m_io.s
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@ -1,60 +0,0 @@
/***************************************************************************
* Copyright (C) 2013 by Henrik Nilsson *
* henrik.nilsson@bytequest.se *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.arch armv7-m
.thumb
.thumb_func
.align 4
/* Inputs:
* r0 buffer address
* r1 NAND data address (byte wide)
* r2 buffer length
*/
read:
ldrb r3, [r1]
strb r3, [r0], #1
subs r2, r2, #1
bne read
done_read:
bkpt #0
.align 4
/* Inputs:
* r0 NAND data address (byte wide)
* r1 buffer address
* r2 buffer length
*/
write:
ldrb r3, [r1], #1
strb r3, [r0]
subs r2, r2, #1
bne write
done_write:
bkpt #0
.end

4
contrib/loaders/flash/at91sam7x/at91sam7x_ocl_flash.script
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@ -1,4 +0,0 @@
soft_reset_halt
load_image at91sam7x_ocl.bin 0x200000
resume 0x200000
flash probe 0

132
contrib/loaders/flash/at91sam7x/at91sam7x_ram.ld
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@ -1,132 +0,0 @@
/****************************************************************************
* Copyright (c) 2006 by Michael Fischer. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of its contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
****************************************************************************
*
* History:
*
* 30.03.06 mifi First Version
****************************************************************************/
ENTRY(ResetHandler)
SEARCH_DIR(.)
/*
* Define stack size here
*/
FIQ_STACK_SIZE = 0x0100;
IRQ_STACK_SIZE = 0x0100;
ABT_STACK_SIZE = 0x0100;
UND_STACK_SIZE = 0x0100;
SVC_STACK_SIZE = 0x0100;
MEMORY
{
ram : org = 0x00200000, len = 64k
}
/*
* Do not change the next code
*/
SECTIONS
{
.text :
{
*(.vectors);
. = ALIGN(4);
*(.init);
. = ALIGN(4);
*(.text);
. = ALIGN(4);
*(.rodata);
. = ALIGN(4);
*(.rodata*);
. = ALIGN(4);
*(.glue_7t);
. = ALIGN(4);
*(.glue_7);
. = ALIGN(4);
etext = .;
} > ram
.data :
{
PROVIDE (__data_start = .);
*(.data)
. = ALIGN(4);
edata = .;
_edata = .;
PROVIDE (__data_end = .);
} > ram
.bss :
{
PROVIDE (__bss_start = .);
*(.bss)
*(COMMON)
. = ALIGN(4);
PROVIDE (__bss_end = .);
. = ALIGN(256);
PROVIDE (__stack_start = .);
PROVIDE (__stack_fiq_start = .);
. += FIQ_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_fiq_end = .);
PROVIDE (__stack_irq_start = .);
. += IRQ_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_irq_end = .);
PROVIDE (__stack_abt_start = .);
. += ABT_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_abt_end = .);
PROVIDE (__stack_und_start = .);
. += UND_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_und_end = .);
PROVIDE (__stack_svc_start = .);
. += SVC_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_svc_end = .);
PROVIDE (__stack_end = .);
PROVIDE (__heap_start = .);
} > ram
}
/*** EOF ***/

223
contrib/loaders/flash/at91sam7x/crt.s
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@ -1,223 +0,0 @@
/****************************************************************************
* Copyright (c) 2006 by Michael Fischer. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of its contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
****************************************************************************
*
* History:
*
* 18.12.06 mifi First Version
* The hardware initialization is based on the startup file
* crtat91sam7x256_rom.S from NutOS 4.2.1.
* Therefore partial copyright by egnite Software GmbH.
****************************************************************************/
/*
* Some defines for the program status registers
*/
ARM_MODE_USER = 0x10 /* Normal User Mode */
ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */
ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */
ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */
ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */
ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */
ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */
ARM_MODE_MASK = 0x1F
I_BIT = 0x80 /* disable IRQ when I bit is set */
F_BIT = 0x40 /* disable IRQ when I bit is set */
/*
* Register Base Address
*/
AIC_BASE = 0xFFFFF000
AIC_EOICR_OFF = 0x130
AIC_IDCR_OFF = 0x124
RSTC_MR = 0xFFFFFD08
RSTC_KEY = 0xA5000000
RSTC_URSTEN = 0x00000001
WDT_BASE = 0xFFFFFD40
WDT_MR_OFF = 0x00000004
WDT_WDDIS = 0x00008000
MC_BASE = 0xFFFFFF00
MC_FMR_OFF = 0x00000060
MC_FWS_1FWS = 0x00480100
.section .vectors,"ax"
.code 32
/****************************************************************************/
/* Vector table and reset entry */
/****************************************************************************/
_vectors:
ldr pc, ResetAddr /* Reset */
ldr pc, UndefAddr /* Undefined instruction */
ldr pc, SWIAddr /* Software interrupt */
ldr pc, PAbortAddr /* Prefetch abort */
ldr pc, DAbortAddr /* Data abort */
ldr pc, ReservedAddr /* Reserved */
ldr pc, IRQAddr /* IRQ interrupt */
ldr pc, FIQAddr /* FIQ interrupt */
ResetAddr: .word ResetHandler
UndefAddr: .word UndefHandler
SWIAddr: .word SWIHandler
PAbortAddr: .word PAbortHandler
DAbortAddr: .word DAbortHandler
ReservedAddr: .word 0
IRQAddr: .word IRQHandler
FIQAddr: .word FIQHandler
.ltorg
.section .init, "ax"
.code 32
.global ResetHandler
.global ExitFunction
.extern main
/****************************************************************************/
/* Reset handler */
/****************************************************************************/
ResetHandler:
/*
* The watchdog is enabled after processor reset. Disable it.
*/
ldr r1, =WDT_BASE
ldr r0, =WDT_WDDIS
str r0, [r1, #WDT_MR_OFF]
/*
* Enable user reset: assertion length programmed to 1ms
*/
ldr r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8))
ldr r1, =RSTC_MR
str r0, [r1, #0]
/*
* Use 2 cycles for flash access.
*/
ldr r1, =MC_BASE
ldr r0, =MC_FWS_1FWS
str r0, [r1, #MC_FMR_OFF]
/*
* Disable all interrupts. Useful for debugging w/o target reset.
*/
ldr r1, =AIC_BASE
mvn r0, #0
str r0, [r1, #AIC_EOICR_OFF]
str r0, [r1, #AIC_IDCR_OFF]
/*
* Setup a stack for each mode
*/
msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
ldr sp, =__stack_und_end
msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */
ldr sp, =__stack_abt_end
msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
ldr sp, =__stack_fiq_end
msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
ldr sp, =__stack_irq_end
msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
ldr sp, =__stack_svc_end
/*
* Clear .bss section
*/
ldr r1, =__bss_start
ldr r2, =__bss_end
ldr r3, =0
bss_clear_loop:
cmp r1, r2
strne r3, [r1], #+4
bne bss_clear_loop
/*
* Jump to main
*/
mrs r0, cpsr
bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */
msr cpsr, r0
mov r0, #0 /* No arguments */
mov r1, #0 /* No arguments */
ldr r2, =main
mov lr, pc
bx r2 /* And jump... */
ExitFunction:
nop
nop
nop
b ExitFunction
/****************************************************************************/
/* Default interrupt handler */
/****************************************************************************/
UndefHandler:
b UndefHandler
SWIHandler:
b SWIHandler
PAbortHandler:
b PAbortHandler
DAbortHandler:
b DAbortHandler
IRQHandler:
b IRQHandler
FIQHandler:
b FIQHandler
.weak ExitFunction
.weak UndefHandler, PAbortHandler, DAbortHandler
.weak IRQHandler, FIQHandler
.ltorg
/*** EOF ***/

51
contrib/loaders/flash/at91sam7x/dcc.c
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@ -1,51 +0,0 @@
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#include "dcc.h"
/* debug channel read (debugger->MCU) */
uint32 dcc_rd(void)
{
volatile uint32 dcc_reg;
do {
asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) :);
} while ((dcc_reg&1) == 0);
asm volatile ("mrc p14, 0, %0, C1, C0" : "=r" (dcc_reg) :);
return dcc_reg;
}
/* debug channel write (MCU->debugger) */
int dcc_wr(uint32 data)
{
volatile uint32 dcc_reg;
do {
asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) :);
/* operation controled by master, cancel operation
upon reception of data for immediate response */
if (dcc_reg&1) return -1;
} while (dcc_reg&2);
asm volatile ("mcr p14, 0, %0, C1, C0" : : "r" (data));
return 0;
}

31
contrib/loaders/flash/at91sam7x/dcc.h
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@ -1,31 +0,0 @@
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#ifndef dccH
#define dccH
#include "platform.h"
/* debug channel read (debugger->MCU) */
uint32 dcc_rd(void);
/* debug channel write (MCU->debugger) */
int dcc_wr(uint32 data);
#endif

107
contrib/loaders/flash/at91sam7x/main.c
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@ -1,107 +0,0 @@
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#include "platform.h"
#include <flash/nor/ocl.h>
#include "dcc.h"
#include "samflash.h"
#define BUFSIZE 1024 /* words, i.e. 4 KiB */
uint32 buffer[1024];
void cmd_flash(uint32 cmd)
{
unsigned int len;
uint32 adr;
uint32 chksum;
unsigned int bi; /* buffer index */
unsigned int bi_start; /* receive start mark */
unsigned int bi_end; /* receive end mark */
unsigned int ofs;
int pagenum;
int result;
adr = dcc_rd();
len = cmd&0xffff;
ofs = adr%flash_page_size;
bi_start = ofs/4;
bi_end = (ofs + len + 3)/4;
if (bi_end > BUFSIZE) {
dcc_wr(OCL_BUFF_OVER);
return;
}
chksum = OCL_CHKS_INIT;
for (bi = 0; bi < bi_end; bi++) chksum^=buffer[bi]=dcc_rd();
if (dcc_rd() != chksum) {
dcc_wr(OCL_CHKS_FAIL);
return;
}
/* fill in unused positions with unprogrammed values */
for (bi = 0; bi < bi_start; bi++) buffer[bi]=0xffffffff;
for (bi = bi_end; bi%flash_page_size; bi++) buffer[bi]=0xffffffff;
result = 0;
pagenum = adr/flash_page_size;
for (bi = 0; bi < bi_end; bi += flash_page_size/4) {
result = flash_page_program(buffer + bi, pagenum++);
if (result) break;
}
/* verify written data */
if (!result) result = flash_verify(adr, len, ((uint8 *)buffer) + ofs);
dcc_wr(OCL_CMD_DONE | result);
}
int main (void)
{
uint32 cmd;
for (;;) {
cmd = dcc_rd();
switch (cmd&OCL_CMD_MASK) {
case OCL_PROBE:
dcc_wr(OCL_CMD_DONE | flash_init());
dcc_wr(0x100000); /* base */
dcc_wr(flash_page_count*flash_page_size); /* size */
dcc_wr(1); /* num_sectors */
dcc_wr(4096 | ((unsigned long) flash_page_size << 16)); /* buflen and bufalign */
break;
case OCL_ERASE_ALL:
dcc_wr(OCL_CMD_DONE | flash_erase_all());
break;
case OCL_FLASH_BLOCK:
cmd_flash(cmd);
break;
default:
/* unknown command */
dcc_wr(OCL_CMD_ERR);
break;
}
}
return(0); /* we shall never get here, just to supress compiler warning */
}

130
contrib/loaders/flash/at91sam7x/makefile
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##############################################################################################
# Start of default section
#
TRGT = arm-elf-
CC = $(TRGT)gcc
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
OBJDUMP = $(TRGT)objdump
MCU = arm7tdmi
# List all default C defines here, like -D_DEBUG=1
DDEFS =
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =
# List all default directories to look for include files here
DINCDIR =
# List the default directory to look for the libraries here
DLIBDIR =
# List all default libraries here
DLIBS =
#
# End of default section
##############################################################################################
##############################################################################################
# Start of user section
#
# Define project name here
PROJECT = at91sam7x_ocl
# Define linker script file here
LDSCRIPT= at91sam7x_ram.ld
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List C source files here
SRC = main.c dcc.c samflash.c
# List ASM source files here
ASRC = crt.s
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
# Define optimisation level here
OPT = -O2
#
# End of user defines
##############################################################################################
INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR))
LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
DEFS = $(DDEFS) $(UDEFS)
ADEFS = $(DADEFS) $(UADEFS)
OBJS = $(ASRC:.s=.o) $(SRC:.c=.o)
LIBS = $(DLIBS) $(ULIBS)
MCFLAGS = -mcpu=$(MCU)
ASFLAGS = $(MCFLAGS) -g -gdwarf-2 -Wa,-amhls=$(<:.s=.lst) $(ADEFS)
CPFLAGS = $(MCFLAGS) $(OPT) -gdwarf-2 -mthumb-interwork -fomit-frame-pointer -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS)
LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR)
# Generate dependency information
#CPFLAGS += -MD -MP -MF .dep/$(@F).d
#
# makefile rules
#
all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).lst
%o : %c
$(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@
%o : %s
$(AS) -c $(ASFLAGS) $< -o $@
%elf: $(OBJS)
$(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
%hex: %elf
$(HEX) $< $@
%bin: %elf
$(BIN) $< $@
%.lst: %.elf
$(OBJDUMP) -h -S $< > $@
clean:
-rm -f $(OBJS)
-rm -f $(PROJECT).elf
-rm -f $(PROJECT).map
-rm -f $(PROJECT).hex
-rm -f $(PROJECT).bin
-rm -f $(PROJECT).lst
-rm -f $(SRC:.c=.c.bak)
-rm -f $(SRC:.c=.lst)
-rm -f $(ASRC:.s=.s.bak)
-rm -f $(ASRC:.s=.lst)
-rm -fR .dep
#
# Include the dependency files, should be the last of the makefile
#
#-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
# *** EOF ***

40
contrib/loaders/flash/at91sam7x/ocl.h
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/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#ifndef OCL_H
#define OCL_H
/* command/response mask */
#define OCL_CMD_MASK 0xFFFF0000L
/* commads */
#define OCL_FLASH_BLOCK 0x0CFB0000L
#define OCL_ERASE_BLOCK 0x0CEB0000L
#define OCL_ERASE_ALL 0x0CEA0000L
#define OCL_PROBE 0x0CBE0000L
/* responses */
#define OCL_CMD_DONE 0x0ACD0000L
#define OCL_CMD_ERR 0x0ACE0000L
#define OCL_CHKS_FAIL 0x0ACF0000L
#define OCL_BUFF_OVER 0x0AB00000L
#define OCL_CHKS_INIT 0xC100CD0CL
#endif /* OCL_H */

46
contrib/loaders/flash/at91sam7x/platform.h
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/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#ifndef platformH
#define platformH
#include "samregs.h"
#define outb(_reg, _val) (*((volatile unsigned char *)(_reg)) = (_val))
#define outw(_reg, _val) (*((volatile unsigned short *)(_reg)) = (_val))
#define outr(_reg, _val) (*((volatile unsigned int *)(_reg)) = (_val))
#define inb(_reg) (*((volatile unsigned char *)(_reg)))
#define inw(_reg) (*((volatile unsigned short *)(_reg)))
#define inr(_reg) (*((volatile unsigned int *)(_reg)))
#define _BV(bit) (1 << (bit))
typedef signed char int8;
typedef unsigned char uint8;
typedef signed short int16;
typedef unsigned short uint16;
typedef signed int int32;
typedef unsigned int uint32;
#endif

196
contrib/loaders/flash/at91sam7x/samflash.c
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@ -1,196 +0,0 @@
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#include "samflash.h"
unsigned int flash_page_count = 1024;
unsigned int flash_page_size = 256;
/* pages per lock bit */
unsigned int flash_lock_pages = 1024/16;
/* detect chip and set loader parameters */
int flash_init(void)
{
unsigned int nvpsiz;
nvpsiz = (inr(DBGU_CIDR) >> 8)&0xf;
switch (nvpsiz) {
case 3:
/* AT91SAM7x32 */
flash_page_count = 256;
flash_page_size = 128;
flash_lock_pages = 256/8;
break;
case 5:
/* AT91SAM7x64 */
flash_page_count = 512;
flash_page_size = 128;
flash_lock_pages = 512/16;
break;
case 7:
/* AT91SAM7x128*/
flash_page_count = 512;
flash_page_size = 256;
flash_lock_pages = 512/8;
break;
case 9:
/* AT91SAM7x256 */
flash_page_count = 1024;
flash_page_size = 256;
flash_lock_pages = 1024/16;
break;
case 10:
/* AT91SAM7x512 */
flash_page_count = 2048;
flash_page_size = 256;
flash_lock_pages = 2048/32;
break;
default:
return FLASH_STAT_INITE;
}
return FLASH_STAT_OK;
}
/* program single flash page */
int flash_page_program(uint32 *data, int page_num)
{
int i;
int efc_ofs;
uint32 *flash_ptr;
uint32 *data_ptr;
/* select proper controller */
if (page_num >= 1024) efc_ofs = 0x10;
else efc_ofs = 0;
/* wait until FLASH is ready, just for sure */
while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
/* calculate page address, only lower 8 bits are used to address the latch,
but the upper part of address is needed for writing to proper EFC */
flash_ptr = (uint32 *)(FLASH_AREA_ADDR + (page_num*flash_page_size));
data_ptr = data;
/* copy data to latch */
for (i = flash_page_size/4; i; i--) {
/* we do not use memcpy to be sure that only 32 bit access is used */
*(flash_ptr++)=*(data_ptr++);
}
/* page number and page write command to FCR */
outr(MC_FCR + efc_ofs, ((page_num&0x3ff) << 8) | MC_KEY | MC_FCMD_WP);
/* wait until it's done */
while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
/* check for errors */
if ((inr(MC_FSR + efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
if ((inr(MC_FSR + efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
#if 0
/* verify written data */
flash_ptr = (uint32 *)(FLASH_AREA_ADDR + (page_num*flash_page_size));
data_ptr = data;
for (i = flash_page_size/4; i; i--) {
if (*(flash_ptr++)!=*(data_ptr++)) return FLASH_STAT_VERIFE;
}
#endif
return FLASH_STAT_OK;
}
int flash_erase_plane(int efc_ofs)
{
unsigned int lockbits;
int page_num;
page_num = 0;
lockbits = inr(MC_FSR + efc_ofs) >> 16;
while (lockbits) {
if (lockbits&1) {
/* wait until FLASH is ready, just for sure */
while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
outr(MC_FCR + efc_ofs, ((page_num&0x3ff) << 8) | 0x5a000004);
/* wait until it's done */
while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
/* check for errors */
if ((inr(MC_FSR + efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
if ((inr(MC_FSR + efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
}
if ((page_num += flash_lock_pages) > flash_page_count) break;
lockbits>>=1;
}
/* wait until FLASH is ready, just for sure */
while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
/* erase all command to FCR */
outr(MC_FCR + efc_ofs, 0x5a000008);
/* wait until it's done */
while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
/* check for errors */
if ((inr(MC_FSR + efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
if ((inr(MC_FSR + efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
/* set no erase before programming */
outr(MC_FMR + efc_ofs, inr(MC_FMR + efc_ofs) | 0x80);
return FLASH_STAT_OK;
}
/* erase whole chip */
int flash_erase_all(void)
{
int result;
if ((result = flash_erase_plane(0)) != FLASH_STAT_OK) return result;
/* the second flash controller, if any */
if (flash_page_count > 1024) result = flash_erase_plane(0x10);
return result;
}
int flash_verify(uint32 adr, unsigned int len, uint8 *src)
{
unsigned char *flash_ptr;
flash_ptr = (uint8 *)FLASH_AREA_ADDR + adr;
for (;len; len--) {
if (*(flash_ptr++)!=*(src++)) return FLASH_STAT_VERIFE;
}
return FLASH_STAT_OK;
}

48
contrib/loaders/flash/at91sam7x/samflash.h
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@ -1,48 +0,0 @@
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#ifndef samflashH
#define samflashH
#include "platform.h"
#define FLASH_AREA_ADDR 0x100000
#define FLASH_STAT_OK 0
#define FLASH_STAT_PROGE 1
#define FLASH_STAT_LOCKE 2
#define FLASH_STAT_VERIFE 3
#define FLASH_STAT_INITE 4
extern unsigned int flash_page_count;
extern unsigned int flash_page_size; /* words */
/* detect chip and set loader parameters */
int flash_init(void);
/* program single flash page */
int flash_page_program(uint32 *data, int page_num);
/* erase whole chip */
int flash_erase_all(void);
/* verify written data */
int flash_verify(uint32 adr, unsigned int len, uint8 *src);
#endif

83
contrib/loaders/flash/at91sam7x/samregs.h
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/*
* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef samregsH
#define samregsH
/*
* Register definitions below copied from NutOS
*/
#define DBGU_BASE 0xFFFFF200 /*!< \brief DBGU base address. */
#define DBGU_CIDR_OFF 0x00000040 /*!< \brief DBGU chip ID register offset. */
#define DBGU_CIDR (DBGU_BASE + DBGU_CIDR_OFF) /*!< \brief DBGU chip ID register. */
#define MC_BASE 0xFFFFFF00 /*!< \brief Memory controller base. */
#define MC_FMR_OFF 0x00000060 /*!< \brief MC flash mode register offset. */
#define MC_FMR (MC_BASE + MC_FMR_OFF) /*!< \brief MC flash mode register address. */
#define MC_FRDY 0x00000001 /*!< \brief Flash ready. */
#define MC_LOCKE 0x00000004 /*!< \brief Lock error. */
#define MC_PROGE 0x00000008 /*!< \brief Programming error. */
#define MC_NEBP 0x00000080 /*!< \brief No erase before programming. */
#define MC_FWS_MASK 0x00000300 /*!< \brief Flash wait state mask. */
#define MC_FWS_1R2W 0x00000000 /*!< \brief 1 cycle for read, 2 for write operations. */
#define MC_FWS_2R3W 0x00000100 /*!< \brief 2 cycles for read, 3 for write operations. */
#define MC_FWS_3R4W 0x00000200 /*!< \brief 3 cycles for read, 4 for write operations. */
#define MC_FWS_4R4W 0x00000300 /*!< \brief 4 cycles for read and write operations. */
#define MC_FMCN_MASK 0x00FF0000 /*!< \brief Flash microsecond cycle number mask. */
#define MC_FCR_OFF 0x00000064 /*!< \brief MC flash command register offset. */
#define MC_FCR (MC_BASE + MC_FCR_OFF) /*!< \brief MC flash command register address. */
#define MC_FCMD_MASK 0x0000000F /*!< \brief Flash command mask. */
#define MC_FCMD_NOP 0x00000000 /*!< \brief No command. */
#define MC_FCMD_WP 0x00000001 /*!< \brief Write page. */
#define MC_FCMD_SLB 0x00000002 /*!< \brief Set lock bit. */
#define MC_FCMD_WPL 0x00000003 /*!< \brief Write page and lock. */
#define MC_FCMD_CLB 0x00000004 /*!< \brief Clear lock bit. */
#define MC_FCMD_EA 0x00000008 /*!< \brief Erase all. */
#define MC_FCMD_SGPB 0x0000000B /*!< \brief Set general purpose NVM bit. */
#define MC_FCMD_CGPB 0x0000000D /*!< \brief Clear general purpose NVM bit. */
#define MC_FCMD_SSB 0x0000000F /*!< \brief Set security bit. */
#define MC_PAGEN_MASK 0x0003FF00 /*!< \brief Page number mask. */
#define MC_KEY 0x5A000000 /*!< \brief Writing protect key. */
#define MC_FSR_OFF 0x00000068 /*!< \brief MC flash status register offset. */
#define MC_FSR (MC_BASE + MC_FSR_OFF) /*!< \brief MC flash status register address. */
#define MC_SECURITY 0x00000010 /*!< \brief Security bit status. */
#endif

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contrib/loaders/flash/cortex-m0.S
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/***************************************************************************
* Copyright (C) 2014 by Angus Gratton *
* Derived from stm32f1x.S:
* Copyright (C) 2011 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* Copyright (C) 2013 by Roman Dmitrienko *
* me@iamroman.org *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
/* Written for NRF51822 (src/flash/nor/nrf51.c) however the NRF NVMC is
* very generic (CPU blocks during flash writes), so this is actually
* just a generic word-oriented copy routine for Cortex-M0 (also
* suitable for Cortex-M0+/M3/M4.)
*
* To assemble:
* arm-none-eabi-gcc -c cortex-m0.S
*
* To disassemble:
* arm-none-eabi-objdump -o cortex-m0.o
*
* Thanks to Jens Bauer for providing advice on some of the tweaks.
*/
/* Params:
* r0 - byte count (in)
* r1 - workarea start
* r2 - workarea end
* r3 - target address
* Clobbered:
* r4 - rp
* r5 - wp, tmp
*/
wait_fifo:
ldr r5, [r1, #0] /* read wp */
cmp r5, #0 /* abort if wp == 0 */
beq exit
ldr r4, [r1, #4] /* read rp */
cmp r4, r5 /* wait until rp != wp */
beq wait_fifo
ldmia r4!, {r5} /* "*target_address++ = *rp++" */
stmia r3!, {r5}
cmp r4, r2 /* wrap rp at end of work area buffer */
bcc no_wrap
mov r4, r1
adds r4, #8 /* skip rp,wp at start of work area */
no_wrap:
str r4, [r1, #4] /* write back rp */
subs r0, #4 /* decrement byte count */
bne wait_fifo /* loop if not done */
exit:
bkpt #0

114
contrib/loaders/flash/efm32.S
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@ -1,114 +0,0 @@
/***************************************************************************
* Copyright (C) 2011 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* Copyright (C) 2013 by Roman Dmitrienko *
* me@iamroman.org *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
/* Params:
* r0 - flash base (in), status (out)
* r1 - count (word-32bit)
* r2 - workarea start
* r3 - workarea end
* r4 - target address
* Clobbered:
* r5 - rp
* r6 - wp, tmp
* r7 - tmp
*/
/* offsets of registers from flash reg base */
#define EFM32_MSC_WRITECTRL_OFFSET 0x008
#define EFM32_MSC_WRITECMD_OFFSET 0x00c
#define EFM32_MSC_ADDRB_OFFSET 0x010
#define EFM32_MSC_WDATA_OFFSET 0x018
#define EFM32_MSC_STATUS_OFFSET 0x01c
#define EFM32_MSC_LOCK_OFFSET 0x03c
/* unlock MSC */
ldr r6, =#0x1b71
str r6, [r0, #EFM32_MSC_LOCK_OFFSET]
/* set WREN to 1 */
movs r6, #1
str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET]
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
/* store address in MSC_ADDRB */
str r4, [r0, #EFM32_MSC_ADDRB_OFFSET]
/* set LADDRIM bit */
movs r6, #1
str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
/* check status for INVADDR and/or LOCKED */
ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
movs r7, #6
tst r6, r7
bne error
/* wait for WDATAREADY */
wait_wdataready:
ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
movs r7, #8
tst r6, r7
beq wait_wdataready
/* load data to WDATA */
ldr r6, [r5]
str r6, [r0, #EFM32_MSC_WDATA_OFFSET]
/* set WRITEONCE bit */
movs r6, #8
str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
adds r5, #4 /* rp++ */
adds r4, #4 /* target_address++ */
/* wait until BUSY flag is reset */
busy:
ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
movs r7, #1
tst r6, r7
bne busy
cmp r5, r3 /* wrap rp at end of buffer */
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4] /* store rp */
subs r1, r1, #1 /* decrement word count */
cmp r1, #0
beq exit /* loop if not done */
b wait_fifo
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0

32
contrib/loaders/flash/fm4/Makefile
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@ -1,32 +0,0 @@
BIN2C = ../../../../src/helper/bin2char.sh
CROSS_COMPILE ?= arm-none-eabi-
CC=$(CROSS_COMPILE)gcc
OBJCOPY=$(CROSS_COMPILE)objcopy
OBJDUMP=$(CROSS_COMPILE)objdump
CFLAGS = -static -nostartfiles -mlittle-endian -Wa,-EL
all: erase.inc write.inc
.PHONY: clean
.INTERMEDIATE: erase.elf write.elf
erase.elf write.elf: fm4.h
%.elf: %.S
$(CC) $(CFLAGS) $< -o $@
%.lst: %.elf
$(OBJDUMP) -S $< > $@
%.bin: %.elf
$(OBJCOPY) -Obinary $< $@
%.inc: %.bin
$(BIN2C) < $< > $@
clean:
-rm -f *.elf *.lst *.bin *.inc

77
contrib/loaders/flash/fm4/erase.S
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@ -1,77 +0,0 @@
/*
* Spansion FM4 flash sector erase algorithm
*
* Copyright (c) 2015 Andreas Färber
*
* Based on S6E2CC_MN709-00007 for S6E2CC/C5/C4/C3/C2/C1 series
*/
#include "fm4.h"
#define RESULT_OKAY 0
#define RESULT_NONE 1
#define RESULT_TIMEOUT 2
.macro busy_wait, res, addr, tmp1, tmp2, tmp3
ldrb \tmp1, [\addr] /* ignore */
1001:
ldrb \tmp1, [\addr]
ldrb \tmp2, [\addr]
and \tmp3, \tmp1, #FLASH_TOGG
and \tmp2, \tmp2, #FLASH_TOGG
cmp \tmp3, \tmp2
beq 1010f
and \tmp2, \tmp1, #FLASH_TLOV
cmp \tmp2, #0
beq 1001b
ldrb \tmp1, [\addr]
ldrb \tmp2, [\addr]
and \tmp3, \tmp1, #FLASH_TOGG
and \tmp2, \tmp2, #FLASH_TOGG
cmp \tmp3, \tmp2
beq 1010f
mov \res, #RESULT_TIMEOUT
bkpt #0
1010:
mov \res, #RESULT_OKAY
.endm
.macro erase, cmdseqaddr1, cmdseqaddr2, sa, res, tmp1, tmp2, tmp3
mov \res, #RESULT_NONE
mov \tmp1, #0xAA
strh \tmp1, [\cmdseqaddr1]
mov \tmp2, #0x55
strh \tmp2, [\cmdseqaddr2]
mov \tmp3, #0x80
strh \tmp3, [\cmdseqaddr1]
strh \tmp1, [\cmdseqaddr1]
strh \tmp2, [\cmdseqaddr2]
mov \tmp3, #0x30
strh \tmp3, [\sa]
busy_wait \res, \sa, \tmp1, \tmp2, \tmp3
.endm
/* r0 = 0xAA8
* r1 = 0x554
* r2 = SA
* r3 = result
*/
erase:
erase r0, r1, r2, r3, r4, r5, r6
bkpt #0
data:

7
contrib/loaders/flash/fm4/erase.inc
View File

@ -1,7 +0,0 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
0x4f,0xf0,0x01,0x03,0x4f,0xf0,0xaa,0x04,0x04,0x80,0x4f,0xf0,0x55,0x05,0x0d,0x80,
0x4f,0xf0,0x80,0x06,0x06,0x80,0x04,0x80,0x0d,0x80,0x4f,0xf0,0x30,0x06,0x16,0x80,
0x14,0x78,0x14,0x78,0x15,0x78,0x04,0xf0,0x40,0x06,0x05,0xf0,0x40,0x05,0xae,0x42,
0x0e,0xd0,0x04,0xf0,0x20,0x05,0x00,0x2d,0xf3,0xd0,0x14,0x78,0x15,0x78,0x04,0xf0,
0x40,0x06,0x05,0xf0,0x40,0x05,0xae,0x42,0x02,0xd0,0x4f,0xf0,0x02,0x03,0x00,0xbe,
0x4f,0xf0,0x00,0x03,0x00,0xbe,

19
contrib/loaders/flash/fm4/fm4.h
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@ -1,19 +0,0 @@
/*
* Spansion FM4 flash macros
*
* Copyright (c) 2015 Andreas Färber
*
* Based on S6E2CC_MN709-00007 for S6E2CC/C5/C4/C3/C2/C1 series
*/
.text
.syntax unified
.cpu cortex-m4
.thumb
.thumb_func
#define FLASH_DPOL (1 << 7)
#define FLASH_TOGG (1 << 6)
#define FLASH_TLOV (1 << 5)
#define FLASH_TOGG2 (1 << 2)

85
contrib/loaders/flash/fm4/write.S
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@ -1,85 +0,0 @@
/*
* Spansion FM4 flash write algorithm
*
* Copyright (c) 2015 Andreas Färber
*
* Based on S6E2CC_MN709-00007 for S6E2CC/C5/C4/C3/C2/C1 series
*/
#include "fm4.h"
#define RESULT_OKAY 0
#define RESULT_NONE 1
#define RESULT_TIMEOUT 2
.macro busy_wait, res, addr, data, tmp1, tmp2, tmp3
ldrb \tmp1, [\addr] /* ignore */
and \tmp2, \data, #FLASH_DPOL
1001:
ldrb \tmp1, [\addr]
and \tmp3, \tmp1, #FLASH_DPOL
cmp \tmp3, \tmp2
beq 1010f
and \tmp3, \tmp1, #FLASH_TLOV
cmp \tmp3, #0
beq 1001b
ldrb \tmp1, [\addr]
and \tmp3, \tmp1, #FLASH_DPOL
cmp \tmp3, \tmp2
beq 1010f
mov \res, #RESULT_TIMEOUT
bkpt #0
1010:
.endm
.macro write_one, res, cmdseqaddr1, cmdseqaddr2, pa, pd, tmp1, tmp2, tmp3
mov \tmp1, #0xAA
strh \tmp1, [\cmdseqaddr1]
mov \tmp1, #0x55
strh \tmp1, [\cmdseqaddr2]
mov \tmp1, #0xA0
strh \tmp1, [\cmdseqaddr1]
strh \pd, [\pa]
busy_wait \res, \pa, \pd, \tmp1, \tmp2, \tmp3
.endm
.macro write, cmdseqaddr1, cmdseqaddr2, dest, src, cnt, res, tmp1, tmp2, tmp3, tmp4
mov \res, #RESULT_NONE
2001:
cbz \cnt, 2010f
ldrh \tmp1, [\src]
write_one \res, \cmdseqaddr1, \cmdseqaddr2, \dest, \tmp1, \tmp2, \tmp3, \tmp4
sub \cnt, \cnt, #1
add \dest, \dest, #2
add \src, \src, #2
b 2001b
2010:
mov \res, #RESULT_OKAY
.endm
/* r0 = 0xAA8
* r1 = 0x554
* r2 = dest
* r3 = src
* r4 = cnt
* r5 = result
*/
write:
write r0, r1, r2, r3, r4, r5, r6, r7, r8, r9
bkpt #0
data:

7
contrib/loaders/flash/fm4/write.inc
View File

@ -1,7 +0,0 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
0x4f,0xf0,0x01,0x05,0x34,0xb3,0x1e,0x88,0x4f,0xf0,0xaa,0x07,0x07,0x80,0x4f,0xf0,
0x55,0x07,0x0f,0x80,0x4f,0xf0,0xa0,0x07,0x07,0x80,0x16,0x80,0x17,0x78,0x06,0xf0,
0x80,0x08,0x17,0x78,0x07,0xf0,0x80,0x09,0xc1,0x45,0x0c,0xd0,0x07,0xf0,0x20,0x09,
0xb9,0xf1,0x00,0x0f,0xf5,0xd0,0x17,0x78,0x07,0xf0,0x80,0x09,0xc1,0x45,0x02,0xd0,
0x4f,0xf0,0x02,0x05,0x00,0xbe,0xa4,0xf1,0x01,0x04,0x02,0xf1,0x02,0x02,0x03,0xf1,
0x02,0x03,0xd7,0xe7,0x4f,0xf0,0x00,0x05,0x00,0xbe,

317
contrib/loaders/flash/fpga/xilinx_bscan_spi.py
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@ -1,317 +0,0 @@
#!/usr/bin/python3
#
# Copyright (C) 2015 Robert Jordens <jordens@gmail.com>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
from migen.fhdl.std import *
from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from mibuild.xilinx.vivado import XilinxVivadoToolchain
from mibuild.xilinx.ise import XilinxISEToolchain
"""
This migen script produces proxy bitstreams to allow programming SPI flashes
behind FPGAs. JTAG signalling is connected directly to SPI signalling. CS_N is
asserted when the JTAG IR contains the USER1 instruction and the state is
SHIFT-DR.
Xilinx bscan cells sample TDO on falling TCK and forward it.
MISO requires sampling on rising CLK and leads to one cycle of latency.
https://github.com/m-labs/migen
"""
class Spartan3(Module):
macro = "BSCAN_SPARTAN3"
def __init__(self, platform):
self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
spi = platform.request("spiflash")
shift = Signal()
tdo = Signal()
sel1 = Signal()
self.comb += [
self.cd_jtag.clk.eq(spi.clk),
spi.cs_n.eq(~shift | ~sel1),
]
self.sync.jtag += tdo.eq(spi.miso)
self.specials += Instance(self.macro,
o_DRCK1=spi.clk, o_SHIFT=shift,
o_TDI=spi.mosi, i_TDO1=tdo, i_TDO2=0,
o_SEL1=sel1)
class Spartan3A(Spartan3):
macro = "BSCAN_SPARTAN3A"
class Spartan6(Module):
def __init__(self, platform):
self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
spi = platform.request("spiflash")
shift = Signal()
tdo = Signal()
sel = Signal()
self.comb += self.cd_jtag.clk.eq(spi.clk), spi.cs_n.eq(~shift | ~sel)
self.sync.jtag += tdo.eq(spi.miso)
self.specials += Instance("BSCAN_SPARTAN6", p_JTAG_CHAIN=1,
o_TCK=spi.clk, o_SHIFT=shift, o_SEL=sel,
o_TDI=spi.mosi, i_TDO=tdo)
class Series7(Module):
def __init__(self, platform):
self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
spi = platform.request("spiflash")
clk = Signal()
shift = Signal()
tdo = Signal()
sel = Signal()
self.comb += self.cd_jtag.clk.eq(clk), spi.cs_n.eq(~shift | ~sel)
self.sync.jtag += tdo.eq(spi.miso)
self.specials += Instance("BSCANE2", p_JTAG_CHAIN=1,
o_SHIFT=shift, o_TCK=clk, o_SEL=sel,
o_TDI=spi.mosi, i_TDO=tdo)
self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0,
i_KEYCLEARB=0, i_PACK=1, i_USRCCLKO=clk,
i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
class XilinxBscanSpi(XilinxPlatform):
pinouts = {
# bitstreams are named by die, package does not matter, speed grade
# should not matter.
# cs_n, clk, mosi, miso, *pullups
"xc3s100e": ("cp132",
["M2", "N12", "N2", "N8"],
"LVCMOS33", Spartan3),
"xc3s1200e": ("fg320",
["U3", "U16", "T4", "N10"],
"LVCMOS33", Spartan3),
"xc3s1400a": ("fg484",
["Y4", "AA20", "AB14", "AB20"],
"LVCMOS33", Spartan3A),
"xc3s1400an": ("fgg484",
["Y4", "AA20", "AB14", "AB20"],
"LVCMOS33", Spartan3A),
"xc3s1600e": ("fg320",
["U3", "U16", "T4", "N10"],
"LVCMOS33", Spartan3),
"xc3s200a": ("fg320",
["V3", "U16", "T11", "V16"],
"LVCMOS33", Spartan3A),
"xc3s200an": ("ftg256",
["T2", "R14", "P10", "T14"],
"LVCMOS33", Spartan3A),
"xc3s250e": ("cp132",
["M2", "N12", "N2", "N8"],
"LVCMOS33", Spartan3),
"xc3s400a": ("fg320",
["V3", "U16", "T11", "V16"],
"LVCMOS33", Spartan3A),
"xc3s400an": ("fgg400",
["Y2", "Y19", "W12", "W18"],
"LVCMOS33", Spartan3A),
"xc3s500e": ("cp132",
["M2", "N12", "N2", "N8"],
"LVCMOS33", Spartan3),
"xc3s50a": ("ft256",
["T2", "R14", "P10", "T14"],
"LVCMOS33", Spartan3A),
"xc3s50an": ("ftg256",
["T2", "R14", "P10", "T14"],
"LVCMOS33", Spartan3A),
"xc3s700a": ("fg400",
["Y2", "Y19", "W12", "W18"],
"LVCMOS33", Spartan3A),
"xc3s700an": ("fgg484",
["Y4", "AA20", "AB14", "AB20"],
"LVCMOS33", Spartan3A),
"xc3sd1800a": ("cs484",
["U7", "V17", "V13", "W17"],
"LVCMOS33", Spartan3A),
"xc3sd3400a": ("cs484",
["U7", "V17", "V13", "W17"],
"LVCMOS33", Spartan3A),
"xc6slx100": ("csg484-2",
["AB5", "W17", "AB17", "Y17", "V13", "W13"],
"LVCMOS33", Spartan6),
"xc6slx100t": ("csg484-2",
["AB5", "W17", "AB17", "Y17", "V13", "W13"],
"LVCMOS33", Spartan6),
"xc6slx150": ("csg484-2",
["AB5", "W17", "AB17", "Y17", "V13", "W13"],
"LVCMOS33", Spartan6),
"xc6slx150t": ("csg484-2",
["AB5", "W17", "AB17", "Y17", "V13", "W13"],
"LVCMOS33", Spartan6),
"xc6slx16": ("cpg196-2",
["P2", "N13", "P11", "N11", "N10", "P10"],
"LVCMOS33", Spartan6),
"xc6slx25": ("csg324-2",
["V3", "R15", "T13", "R13", "T14", "V14"],
"LVCMOS33", Spartan6),
"xc6slx25t": ("csg324-2",
["V3", "R15", "T13", "R13", "T14", "V14"],
"LVCMOS33", Spartan6),
"xc6slx45": ("csg324-2",
["V3", "R15", "T13", "R13", "T14", "V14"],
"LVCMOS33", Spartan6),
"xc6slx45t": ("csg324-2",
["V3", "R15", "T13", "R13", "T14", "V14"],
"LVCMOS33", Spartan6),
"xc6slx4": ("cpg196-2",
["P2", "N13", "P11", "N11", "N10", "P10"],
"LVCMOS33", Spartan6),
"xc6slx4t": ("qg144-2",
["P38", "P70", "P64", "P65", "P62", "P61"],
"LVCMOS33", Spartan6),
"xc6slx75": ("csg484-2",
["AB5", "W17", "AB17", "Y17", "V13", "W13"],
"LVCMOS33", Spartan6),
"xc6slx75t": ("csg484-2",
["AB5", "W17", "AB17", "Y17", "V13", "W13"],
"LVCMOS33", Spartan6),
"xc6slx9": ("cpg196-2",
["P2", "N13", "P11", "N11", "N10", "P10"],
"LVCMOS33", Spartan6),
"xc6slx9t": ("qg144-2",
["P38", "P70", "P64", "P65", "P62", "P61"],
"LVCMOS33", Spartan6),
"xc7a100t": ("csg324-1",
["L13", None, "K17", "K18", "L14", "M14"],
"LVCMOS25", Series7),
"xc7a15t": ("cpg236-1",
["K19", None, "D18", "D19", "G18", "F18"],
"LVCMOS25", Series7),
"xc7a200t": ("fbg484-1",
["T19", None, "P22", "R22", "P21", "R21"],
"LVCMOS25", Series7),
"xc7a35t": ("cpg236-1",
["K19", None, "D18", "D19", "G18", "F18"],
"LVCMOS25", Series7),
"xc7a50t": ("cpg236-1",
["K19", None, "D18", "D19", "G18", "F18"],
"LVCMOS25", Series7),
"xc7a75t": ("csg324-1",
["L13", None, "K17", "K18", "L14", "M14"],
"LVCMOS25", Series7),
"xc7k160t": ("fbg484-1",
["L16", None, "H18", "H19", "G18", "F19"],
"LVCMOS25", Series7),
"xc7k325t": ("fbg676-1",
["C23", None, "B24", "A25", "B22", "A22"],
"LVCMOS25", Series7),
"xc7k355t": ("ffg901-1",
["V26", None, "R30", "T30", "R28", "T28"],
"LVCMOS25", Series7),
"xc7k410t": ("fbg676-1",
["C23", None, "B24", "A25", "B22", "A22"],
"LVCMOS25", Series7),
"xc7k420t": ("ffg1156-1",
["V30", None, "AA33", "AA34", "Y33", "Y34"],
"LVCMOS25", Series7),
"xc7k480t": ("ffg1156-1",
["V30", None, "AA33", "AA34", "Y33", "Y34"],
"LVCMOS25", Series7),
"xc7k70t": ("fbg484-1",
["L16", None, "H18", "H19", "G18", "F19"],
"LVCMOS25", Series7),
"xc7v2000t": ("fhg1761-1",
["AL36", None, "AM36", "AN36", "AJ36", "AJ37"],
"LVCMOS18", Series7),
"xc7v585t": ("ffg1157-1",
["AL33", None, "AN33", "AN34", "AK34", "AL34"],
"LVCMOS18", Series7),
"xc7vh580t": ("flg1155-1",
["AL28", None, "AE28", "AF28", "AJ29", "AJ30"],
"LVCMOS18", Series7),
"xc7vh870t": ("flg1932-1",
["V32", None, "T33", "R33", "U31", "T31"],
"LVCMOS18", Series7),
"xc7vx1140t": ("flg1926-1",
["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
"LVCMOS18", Series7),
"xc7vx330t": ("ffg1157-1",
["AL33", None, "AN33", "AN34", "AK34", "AL34"],
"LVCMOS18", Series7),
"xc7vx415t": ("ffg1157-1",
["AL33", None, "AN33", "AN34", "AK34", "AL34"],
"LVCMOS18", Series7),
"xc7vx485t": ("ffg1157-1",
["AL33", None, "AN33", "AN34", "AK34", "AL34"],
"LVCMOS18", Series7),
"xc7vx550t": ("ffg1158-1",
["C24", None, "A23", "A24", "B26", "A26"],
"LVCMOS18", Series7),
"xc7vx690t": ("ffg1157-1",
["AL33", None, "AN33", "AN34", "AK34", "AL34"],
"LVCMOS18", Series7),
"xc7vx980t": ("ffg1926-1",
["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
"LVCMOS18", Series7),
}
def __init__(self, device, pins, std):
cs_n, clk, mosi, miso = pins[:4]
io = ["spiflash", 0,
Subsignal("cs_n", Pins(cs_n)),
Subsignal("mosi", Pins(mosi)),
Subsignal("miso", Pins(miso), Misc("PULLUP")),
IOStandard(std),
]
if clk:
io.append(Subsignal("clk", Pins(clk)))
for i, p in enumerate(pins[4:]):
io.append(Subsignal("pullup{}".format(i), Pins(p), Misc("PULLUP")))
XilinxPlatform.__init__(self, device, [io])
if isinstance(self.toolchain, XilinxVivadoToolchain):
self.toolchain.bitstream_commands.append(
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]"
)
elif isinstance(self.toolchain, XilinxISEToolchain):
self.toolchain.bitgen_opt += " -g compress"
@classmethod
def make(cls, device, errors=False):
pkg, pins, std, Top = cls.pinouts[device]
platform = cls("{}-{}".format(device, pkg), pins, std)
top = Top(platform)
name = "bscan_spi_{}".format(device)
dir = "build_{}".format(device)
try:
platform.build(top, build_name=name, build_dir=dir)
except Exception as e:
print("ERROR: build failed for {}: {}".format(device, e))
if errors:
raise
if __name__ == "__main__":
import argparse
import multiprocessing
p = argparse.ArgumentParser(description="build bscan_spi bitstreams "
"for openocd jtagspi flash driver")
p.add_argument("device", nargs="*",
default=sorted(list(XilinxBscanSpi.pinouts)),
help="build for these devices (default: %(default)s)")
p.add_argument("-p", "--parallel", default=1, type=int,
help="number of parallel builds (default: %(default)s)")
args = p.parse_args()
pool = multiprocessing.Pool(args.parallel)
pool.map(XilinxBscanSpi.make, args.device, chunksize=1)

112
contrib/loaders/flash/k1921vk01t.S
View File

@ -1,112 +0,0 @@
/***************************************************************************
* Copyright (C) 2015 by Bogdan Kolbov *
* kolbov@niiet.ru *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m4
.thumb
.thumb_func
/* K1921VK01T has 128-bitwidth flash, so it`s able to load 4x32-bit words at the time.
* And only after all words loaded we can start write
*/
/* Registers addresses */
#define FLASH_FMA 0x00 /* Address reg */
#define FLASH_FMD1 0x04 /* Data1 reg */
#define FLASH_FMC 0x08 /* Command reg */
#define FLASH_FCIS 0x0C /* Operation Status reg */
#define FLASH_FCIC 0x14 /* Operation Status Clear reg */
#define FLASH_FMD2 0x50 /* Data2 reg */
#define FLASH_FMD3 0x54 /* Data3 reg */
#define FLASH_FMD4 0x58 /* Data4 reg*/
/* Params:
* r0 - write cmd (in), status (out)
* r1 - count
* r2 - workarea start
* r3 - workarea end
* r4 - target address
* Clobbered:
* r5 - rp
* r6 - wp, tmp
* r7 - flash base
*/
ldr r7, =#0xA001C000 /* Flash reg base*/
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
load_data:
ldr r6, [r5] /* read data1 */
str r6, [r7, #FLASH_FMD1]
adds r5, #4
ldr r6, [r5] /* read data2 */
str r6, [r7, #FLASH_FMD2]
adds r5, #4
ldr r6, [r5] /* read data3 */
str r6, [r7, #FLASH_FMD3]
adds r5, #4
ldr r6, [r5] /* read data4 */
str r6, [r7, #FLASH_FMD4]
adds r5, #4
start_write:
str r4, [r7, #FLASH_FMA] /* set addr */
adds r4, #16
str r0, [r7, #FLASH_FMC] /* write cmd */
busy:
ldr r6, [r7, #FLASH_FCIS] /* wait until flag set */
cmp r6, #0x0
beq busy
cmp r6, #2 /* check the error bit */
beq error
movs r6, #1 /* clear flags */
str r6, [r7, #FLASH_FCIC]
cmp r5, r3 /* wrap rp at end of buffer */
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4] /* store rp */
subs r1, r1, #1 /* decrement 16-byte block count */
cmp r1, #0
beq exit /* loop if not done */
b wait_fifo
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0

21
contrib/loaders/flash/kinetis_ke/Makefile
View File

@ -1,21 +0,0 @@
BIN2C = ../../../../src/helper/bin2char.sh
CROSS_COMPILE ?= arm-none-eabi-
AS = $(CROSS_COMPILE)as
OBJCOPY = $(CROSS_COMPILE)objcopy
AFLAGS = -EL
all: kinetis_ke_flash.inc kinetis_ke_watchdog.inc
%.elf: %.s
$(AS) $(AFLAGS) $< -o $@
%.bin: %.elf
$(OBJCOPY) -Obinary $< $@
%.inc: %.bin
$(BIN2C) < $< > $@
clean:
-rm -f *.elf *.bin *.inc

15
contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.inc
View File

@ -1,15 +0,0 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
0x16,0x68,0x00,0x2e,0xfe,0xd0,0x55,0x68,0xb5,0x42,0xf9,0xd0,0x2f,0x4e,0x30,0x27,
0x37,0x70,0x2f,0x4e,0x00,0x27,0x37,0x70,0x2e,0x4e,0x06,0x27,0x37,0x70,0x07,0x0c,
0x2d,0x4e,0x37,0x70,0x2a,0x4e,0x01,0x27,0x37,0x70,0xc7,0xb2,0x2a,0x4e,0x37,0x70,
0x07,0x0a,0x28,0x4e,0x37,0x70,0x26,0x4e,0x02,0x27,0x37,0x70,0x6f,0x78,0x25,0x4e,
0x37,0x70,0x2f,0x78,0x24,0x4e,0x37,0x70,0x21,0x4e,0x03,0x27,0x37,0x70,0xef,0x78,
0x20,0x4e,0x37,0x70,0xaf,0x78,0x20,0x4e,0x37,0x70,0x01,0x39,0x04,0x30,0x04,0x35,
0x9d,0x42,0x01,0xd3,0x15,0x1c,0x08,0x35,0x00,0x29,0x1b,0xd0,0x16,0x68,0xae,0x42,
0x18,0xd0,0x17,0x4e,0x04,0x27,0x37,0x70,0x6f,0x78,0x16,0x4e,0x37,0x70,0x2f,0x78,
0x15,0x4e,0x37,0x70,0x12,0x4e,0x05,0x27,0x37,0x70,0xef,0x78,0x11,0x4e,0x37,0x70,
0xaf,0x78,0x11,0x4e,0x37,0x70,0x01,0x39,0x04,0x30,0x04,0x35,0x9d,0x42,0x01,0xd3,
0x15,0x1c,0x08,0x35,0x09,0x4e,0x80,0x27,0x37,0x70,0x08,0x4e,0x36,0x78,0x3e,0x42,
0xfb,0xd0,0x30,0x27,0x3e,0x42,0x04,0xd1,0x00,0x26,0x55,0x60,0x00,0x29,0x02,0xd0,
0x9e,0xe7,0x00,0x20,0x50,0x60,0x30,0x1c,0x00,0xbe,0xc0,0x46,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

184
contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.s
View File

@ -1,184 +0,0 @@
/***************************************************************************
* Copyright (C) 2015 by Ivan Meleca *
* ivan@artekit.eu *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
***************************************************************************/
/* Params:
* r0 = flash destination address, status
* r1 = longword count
* r2 = workarea start address
* r3 = workarea end address
*/
.text
.cpu cortex-m0plus
.code 16
.thumb_func
.align 2
/* r5 = rp
* r6 = wp, tmp
* r7 = tmp
*/
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
ldr r6, fstat /* Clear error flags */
mov r7, #48
strb r7, [r6]
ldr r6, fccobix /* FCCOBIX = 0 */
mov r7, #0
strb r7, [r6]
ldr r6, fccobhi /* Program FLASH command */
mov r7, #6 /* FCCOBHI = 6 */
strb r7, [r6]
lsr r7, r0, #16 /* FCCOBLO = flash destination address >> 16 */
ldr r6, fccoblo
strb r7, [r6]
ldr r6, fccobix /* Index for lower byte address bits[15:0] */
mov r7, #1
strb r7, [r6] /* FCCOBIX = 1*/
uxtb r7, r0 /* Memory address bits[15:0] */
ldr r6, fccoblo
strb r7, [r6] /* FCCOBLO = flash destination address */
lsr r7, r0, #8
ldr r6, fccobhi
strb r7, [r6] /* FCCOBHI = flash destination address >> 8 */
ldr r6, fccobix /* FCCOBIX = 2 */
mov r7, #2
strb r7, [r6]
ldrb r7, [r5, #1] /* FCCOBHI = rp >> 8 */
ldr r6, fccobhi
strb r7, [r6]
ldrb r7, [r5] /* FCCOBLO = rp */
ldr r6, fccoblo
strb r7, [r6]
ldr r6, fccobix /* FCCOBIX = 3 */
mov r7, #3
strb r7, [r6]
ldrb r7, [r5, #3] /* FCCOBHI = rp >> 24 */
ldr r6, fccobhi
strb r7, [r6]
ldrb r7, [r5, #2] /* FCCOBLO = rp >> 16 */
ldr r6, fccoblo
strb r7, [r6]
sub r1, r1, #1 /* Two words (4 bytes) queued, decrement counter */
add r0, r0, #4 /* flash address += 4 */
add r5, r5, #4 /* rp += 4 */
cmp r5, r3 /* Wrap? */
bcc no_wrap
mov r5, r2
add r5, r5, #8
no_wrap:
cmp r1, #0 /* Done? */
beq execute
ldr r6, [r2, #0] /* read wp */
cmp r6, r5
beq execute /* execute if rp == wp */
ldr r6, fccobix /* FCCOBIX = 4 */
mov r7, #4
strb r7, [r6]
ldrb r7, [r5, #1] /* FCCOBHI = rp >> 8 */
ldr r6, fccobhi
strb r7, [r6]
ldrb r7, [r5] /* FCCOBLO = rp */
ldr r6, fccoblo
strb r7, [r6]
ldr r6, fccobix /* FCCOBIX = 5 */
mov r7, #5
strb r7, [r6]
ldrb r7, [r5, #3] /* FCCOBHI = rp >> 24 */
ldr r6, fccobhi
strb r7, [r6]
ldrb r7, [r5, #2] /* FCCOBLO = rp >> 16 */
ldr r6, fccoblo
strb r7, [r6]
sub r1, r1, #1 /* Two words (4 bytes) queued, decrement counter */
add r0, r0, #4 /* flash address += 4 */
add r5, r5, #4 /* rp += 4 */
cmp r5, r3 /* Wrap? */
bcc execute
mov r5, r2
add r5, r5, #8
execute:
ldr r6, fstat /* Launch the command */
mov r7, #128
strb r7, [r6]
wait_busy:
ldr r6, fstat
ldrb r6, [r6] /* Wait until finished */
tst r6, r7
beq wait_busy
mov r7, #48 /* Check error */
tst r6, r7
bne error
mov r6, #0 /* Clear error */
str r5, [r2, #4] /* Store rp */
cmp r1, #0 /* Done? */
beq done
b wait_fifo
error:
mov r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
done:
mov r0, r6 /* Set result code */
bkpt #0
.align 2
fstat:
.word 0
fccobix:
.word 0
fccobhi:
.word 0
fccoblo:
.word 0

4
contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.inc
View File

@ -1,4 +0,0 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
0x07,0x4b,0x7f,0x22,0x1d,0x78,0x5c,0x78,0x2a,0x40,0x06,0x4d,0x98,0x88,0xd9,0x88,
0x5d,0x80,0x05,0x4d,0x5d,0x80,0x5c,0x70,0x98,0x80,0xd9,0x80,0x1a,0x70,0x00,0xbe,
0x00,0x20,0x05,0x40,0xc5,0x20,0x00,0x00,0xd9,0x28,0x00,0x00,

47
contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.s
View File

@ -1,47 +0,0 @@
/***************************************************************************
* Copyright (C) 2015 by Ivan Meleca *
* ivan@artekit.eu *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
***************************************************************************/
.text
.cpu cortex-m0plus
.code 16
.thumb_func
.align 2
ldr r3, wdog_cs1
mov r2, #127
ldrb r5, [r3]
ldrb r4, [r3, #1]
and r2, r5
ldr r5, unlock1
ldrh r0, [r3, #4]
ldrh r1, [r3, #6]
strh r5, [r3, #2]
ldr r5, unlock2
strh r5, [r3, #2]
strb r4, [r3, #1]
strh r0, [r3, #4]
strh r1, [r3, #6]
strb r2, [r3]
bkpt #0
.align 2
wdog_cs1:
.word 0x40052000 // Watchdog Control and Status Register 1
unlock1:
.word 0x20C5 // 1st unlock word
unlock2:
.word 0x28D9 // 2nd unlock word

176
contrib/loaders/flash/lpcspifi_erase.S
View File

@ -1,176 +0,0 @@
/***************************************************************************
* Copyright (C) 2012 by George Harris *
* george@luminairecoffee.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = start address, status (out)
* r1 = count
* r2 = erase command
* r3 = block size
*/
#define SSP_BASE_HIGH 0x4008
#define SSP_BASE_LOW 0x3000
#define SSP_CR0_OFFSET 0x00
#define SSP_CR1_OFFSET 0x04
#define SSP_DATA_OFFSET 0x08
#define SSP_CPSR_OFFSET 0x10
#define SSP_SR_OFFSET 0x0c
#define SSP_CLOCK_BASE_HIGH 0x4005
#define SSP_CLOCK_BASE_LOW 0x0000
#define SSP_BRANCH_CLOCK_BASE_HIGH 0x4005
#define SSP_BRANCH_CLOCK_BASE_LOW 0x2000
#define SSP_BASE_CLOCK_OFFSET 0x94
#define SSP_BRANCH_CLOCK_OFFSET 0x700
#define IOCONFIG_BASE_HIGH 0x4008
#define IOCONFIG_BASE_LOW 0x6000
#define IOCONFIG_SCK_OFFSET 0x18c
#define IOCONFIG_HOLD_OFFSET 0x190
#define IOCONFIG_WP_OFFSET 0x194
#define IOCONFIG_MISO_OFFSET 0x198
#define IOCONFIG_MOSI_OFFSET 0x19c
#define IOCONFIG_CS_OFFSET 0x1a0
#define IO_BASE_HIGH 0x400f
#define IO_BASE_LOW 0x4000
#define IO_CS_OFFSET 0xab
#define IODIR_BASE_HIGH 0x400f
#define IODIR_BASE_LOW 0x6000
#define IO_CS_DIR_OFFSET 0x14
setup: /* Initialize SSP pins and module */
mov.w r10, #IOCONFIG_BASE_LOW
movt r10, #IOCONFIG_BASE_HIGH
mov.w r8, #0xea
str.w r8, [r10, #IOCONFIG_SCK_OFFSET] /* Configure SCK pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_HOLD_OFFSET] /* Configure /HOLD pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_WP_OFFSET] /* Configure /WP pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MISO_OFFSET] /* Configure MISO pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MOSI_OFFSET] /* Configure MOSI pin function */
mov.w r8, #0x44
str.w r8, [r10, #IOCONFIG_CS_OFFSET] /* Configure CS pin function */
mov.w r10, #IODIR_BASE_LOW
movt r10, #IODIR_BASE_HIGH
mov.w r8, #0x800
str r8, [r10, #IO_CS_DIR_OFFSET] /* Set CS as output */
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
mov.w r8, #0xff
str.w r8, [r10, #IO_CS_OFFSET] /* Set CS high */
mov.w r10, #SSP_CLOCK_BASE_LOW
movt r10, #SSP_CLOCK_BASE_HIGH
mov.w r8, #0x0000
movt r8, #0x0100
str.w r8, [r10, #SSP_BASE_CLOCK_OFFSET] /* Configure SSP0 base clock (use 12 MHz IRC) */
mov.w r10, #SSP_BRANCH_CLOCK_BASE_LOW
movt r10, #SSP_BRANCH_CLOCK_BASE_HIGH
mov.w r8, #0x01
str.w r8, [r10, #SSP_BRANCH_CLOCK_OFFSET] /* Configure (enable) SSP0 branch clock */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
mov.w r8, #0x07
str.w r8, [r10, #SSP_CR0_OFFSET] /* Set clock postscale */
mov.w r8, #0x02
str.w r8, [r10, #SSP_CPSR_OFFSET] /* Set clock prescale */
str.w r8, [r10, #SSP_CR1_OFFSET] /* Enable SSP in SPI mode */
write_enable:
bl cs_down
mov.w r9, #0x06 /* Send the write enable command */
bl write_data
bl cs_up
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x02 /* If the WE bit isn't set, we have a problem. */
beq error
erase:
bl cs_down
mov.w r9, r2 /* Send the erase command */
bl write_data
write_address:
lsr r9, r0, #16 /* Send the current 24-bit write address, MSB first */
bl write_data
lsr r9, r0, #8
bl write_data
mov.w r9, r0
bl write_data
bl cs_up
wait_flash_busy: /* Wait for the flash to finish the previous erase */
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x01 /* If it isn't done, keep waiting */
bne wait_flash_busy
subs r1, r1, #1 /* decrement count */
cbz r1, exit /* Exit if we have written everything */
add r0, r3 /* Move the address up by the block size */
b write_enable /* Start a new block erase */
write_data: /* Send/receive 1 byte of data over SSP */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
str.w r9, [r10, #SSP_DATA_OFFSET] /* Write supplied data to the SSP data reg */
wait_transmit:
ldr r9, [r10, #SSP_SR_OFFSET] /* Check SSP status */
tst r9, #0x0010 /* Check if BSY bit is set */
bne wait_transmit /* If still transmitting, keep waiting */
ldr r9, [r10, #SSP_DATA_OFFSET] /* Load received data */
bx lr /* Exit subroutine */
cs_up:
mov.w r8, #0xff
b cs_write
cs_down:
mov.w r8, #0x0000
cs_write:
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
str.w r8, [r10, #IO_CS_OFFSET]
bx lr
error:
movs r0, #0
exit:
bkpt #0x00
.end

102
contrib/loaders/flash/lpcspifi_init.S
View File

@ -1,102 +0,0 @@
/***************************************************************************
* Copyright (C) 2012 by George Harris *
* george@luminairecoffee.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/***************************************************************************
* This is an algorithm for the LPC43xx family (and probably the LPC18xx *
* family as well, though they have not been tested) that will initialize *
* memory-mapped SPI flash accesses. Unfortunately NXP has published *
* neither the ROM source code that performs this initialization nor the *
* register descriptions necessary to do so, so this code is necessary to *
* call into the ROM SPIFI API. *
***************************************************************************/
.text
.syntax unified
.arch armv7-m
.thumb
.thumb_func
.align 2
/*
* Params :
* r0 = spifi clock speed
*/
#define IOCONFIG_BASE_HIGH 0x4008
#define IOCONFIG_BASE_LOW 0x6000
#define IOCONFIG_SCK_OFFSET 0x18c
#define IOCONFIG_HOLD_OFFSET 0x190
#define IOCONFIG_WP_OFFSET 0x194
#define IOCONFIG_MISO_OFFSET 0x198
#define IOCONFIG_MOSI_OFFSET 0x19c
#define IOCONFIG_CS_OFFSET 0x1a0
#define SPIFI_ROM_TABLE_BASE_HIGH 0x1040
#define SPIFI_ROM_TABLE_BASE_LOW 0x0118
code:
mov.w r8, r0
sub sp, #0x84
add r7, sp, #0x0
/* Initialize SPIFI pins */
mov.w r3, #IOCONFIG_BASE_LOW
movt r3, #IOCONFIG_BASE_HIGH
mov.w r2, #0xf3
str.w r2, [r3, #IOCONFIG_SCK_OFFSET]
mov.w r3, #IOCONFIG_BASE_LOW
movt r3, #IOCONFIG_BASE_HIGH
mov.w r2, #IOCONFIG_BASE_LOW
movt r2, #IOCONFIG_BASE_HIGH
mov.w r1, #IOCONFIG_BASE_LOW
movt r1, #IOCONFIG_BASE_HIGH
mov.w r0, #IOCONFIG_BASE_LOW
movt r0, #IOCONFIG_BASE_HIGH
mov.w r4, #0xd3
str.w r4, [r0, #IOCONFIG_MOSI_OFFSET]
mov r0, r4
str.w r0, [r1, #IOCONFIG_MISO_OFFSET]
mov r1, r0
str.w r1, [r2, #IOCONFIG_WP_OFFSET]
str.w r1, [r3, #IOCONFIG_HOLD_OFFSET]
mov.w r3, #IOCONFIG_BASE_LOW
movt r3, #IOCONFIG_BASE_HIGH
mov.w r2, #0x13
str.w r2, [r3, #IOCONFIG_CS_OFFSET]
/* Perform SPIFI init. See spifi_rom_api.h (in NXP lpc43xx driver package) for details */
/* on initialization arguments. */
movw r3, #SPIFI_ROM_TABLE_BASE_LOW /* The ROM API table is located @ 0x10400118, and */
movt r3, #SPIFI_ROM_TABLE_BASE_HIGH /* the first pointer in the struct is to the init function. */
ldr r3, [r3, #0x0]
ldr r4, [r3, #0x0] /* Grab the init function pointer from the table */
/* Set up function arguments */
movw r0, #0x3b4
movt r0, #0x1000 /* Pointer to a SPIFI data struct that we don't care about */
mov.w r1, #0x3 /* "csHigh". Not 100% sure what this does. */
mov.w r2, #0xc0 /* The configuration word: S_RCVCLOCK | S_FULLCLK */
mov.w r3, r8 /* SPIFI clock speed (12MHz) */
blx r4 /* Call the init function */
b done
done:
bkpt #0
.end

222
contrib/loaders/flash/lpcspifi_write.S
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@ -1,222 +0,0 @@
/***************************************************************************
* Copyright (C) 2012 by George Harris *
* george@luminairecoffee.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address (offset from flash base)
* r3 = count (bytes)
* r4 = page size
* Clobbered:
* r7 - rp
* r8 - wp, tmp
* r9 - send/receive data
* r10 - temp
* r11 - current page end address
*/
/*
* This code is embedded within: src/flash/nor/lpcspifi.c as a "C" array.
*
* To rebuild:
* arm-none-eabi-gcc -c lpcspifi_write.S
* arm-none-eabi-objcopy -O binary lpcspifi_write.o lpcspifi_write.bin
* xxd -c 8 -i lpcspifi_write.bin > lpcspifi_write.txt
*
* Then read and edit this result into the "C" source.
*/
#define SSP_BASE_HIGH 0x4008
#define SSP_BASE_LOW 0x3000
#define SSP_CR0_OFFSET 0x00
#define SSP_CR1_OFFSET 0x04
#define SSP_DATA_OFFSET 0x08
#define SSP_CPSR_OFFSET 0x10
#define SSP_SR_OFFSET 0x0c
#define SSP_CLOCK_BASE_HIGH 0x4005
#define SSP_CLOCK_BASE_LOW 0x0000
#define SSP_BRANCH_CLOCK_BASE_HIGH 0x4005
#define SSP_BRANCH_CLOCK_BASE_LOW 0x2000
#define SSP_BASE_CLOCK_OFFSET 0x94
#define SSP_BRANCH_CLOCK_OFFSET 0x700
#define IOCONFIG_BASE_HIGH 0x4008
#define IOCONFIG_BASE_LOW 0x6000
#define IOCONFIG_SCK_OFFSET 0x18c
#define IOCONFIG_HOLD_OFFSET 0x190
#define IOCONFIG_WP_OFFSET 0x194
#define IOCONFIG_MISO_OFFSET 0x198
#define IOCONFIG_MOSI_OFFSET 0x19c
#define IOCONFIG_CS_OFFSET 0x1a0
#define IO_BASE_HIGH 0x400f
#define IO_BASE_LOW 0x4000
#define IO_CS_OFFSET 0xab
#define IODIR_BASE_HIGH 0x400f
#define IODIR_BASE_LOW 0x6000
#define IO_CS_DIR_OFFSET 0x14
setup: /* Initialize SSP pins and module */
mov.w r10, #IOCONFIG_BASE_LOW
movt r10, #IOCONFIG_BASE_HIGH
mov.w r8, #0xea
str.w r8, [r10, #IOCONFIG_SCK_OFFSET] /* Configure SCK pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_HOLD_OFFSET] /* Configure /HOLD pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_WP_OFFSET] /* Configure /WP pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MISO_OFFSET] /* Configure MISO pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MOSI_OFFSET] /* Configure MOSI pin function */
mov.w r8, #0x44
str.w r8, [r10, #IOCONFIG_CS_OFFSET] /* Configure CS pin function */
mov.w r10, #IODIR_BASE_LOW
movt r10, #IODIR_BASE_HIGH
mov.w r8, #0x800
str r8, [r10, #IO_CS_DIR_OFFSET] /* Set CS as output */
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
mov.w r8, #0xff
str.w r8, [r10, #IO_CS_OFFSET] /* Set CS high */
mov.w r10, #SSP_CLOCK_BASE_LOW
movt r10, #SSP_CLOCK_BASE_HIGH
mov.w r8, #0x0000
movt r8, #0x0100
str.w r8, [r10, #SSP_BASE_CLOCK_OFFSET] /* Configure SSP0 base clock (use 12 MHz IRC) */
mov.w r10, #SSP_BRANCH_CLOCK_BASE_LOW
movt r10, #SSP_BRANCH_CLOCK_BASE_HIGH
mov.w r8, #0x01
str.w r8, [r10, #SSP_BRANCH_CLOCK_OFFSET] /* Configure (enable) SSP0 branch clock */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
mov.w r8, #0x07
str.w r8, [r10, #SSP_CR0_OFFSET] /* Set clock postscale */
mov.w r8, #0x02
str.w r8, [r10, #SSP_CPSR_OFFSET] /* Set clock prescale */
str.w r8, [r10, #SSP_CR1_OFFSET] /* Enable SSP in SPI mode */
mov.w r11, #0x00
find_next_page_boundary:
add r11, r4 /* Increment to the next page */
cmp r11, r2
/* If we have not reached the next page boundary after the target address, keep going */
bls find_next_page_boundary
write_enable:
bl cs_down
mov.w r9, #0x06 /* Send the write enable command */
bl write_data
bl cs_up
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x02 /* If the WE bit isn't set, we have a problem. */
beq error
page_program:
bl cs_down
mov.w r9, #0x02 /* Send the page program command */
bl write_data
write_address:
lsr r9, r2, #16 /* Send the current 24-bit write address, MSB first */
bl write_data
lsr r9, r2, #8
bl write_data
mov.w r9, r2
bl write_data
wait_fifo:
ldr r8, [r0] /* read the write pointer */
cmp r8, #0 /* if it's zero, we're gonzo */
beq exit
ldr r7, [r0, #4] /* read the read pointer */
cmp r7, r8 /* wait until they are not equal */
beq wait_fifo
write:
ldrb r9, [r7], #0x01 /* Load one byte from the FIFO, increment the read pointer by 1 */
bl write_data /* send the byte to the flash chip */
cmp r7, r1 /* wrap the read pointer if it is at the end */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store the new read pointer */
subs r3, r3, #1 /* decrement count */
cbz r3, exit /* Exit if we have written everything */
add r2, #1 /* Increment flash address by 1 */
cmp r11, r2 /* See if we have reached the end of a page */
bne wait_fifo /* If not, keep writing bytes */
bl cs_up /* Otherwise, end the command and keep going w/ the next page */
add r11, r4 /* Move up the end-of-page address by the page size*/
wait_flash_busy: /* Wait for the flash to finish the previous page write */
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x01 /* If it isn't done, keep waiting */
bne wait_flash_busy
b write_enable /* If it is done, start a new page write */
write_data: /* Send/receive 1 byte of data over SSP */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
str.w r9, [r10, #SSP_DATA_OFFSET] /* Write supplied data to the SSP data reg */
wait_transmit:
ldr r9, [r10, #SSP_SR_OFFSET] /* Check SSP status */
tst r9, #0x0010 /* Check if BSY bit is set */
bne wait_transmit /* If still transmitting, keep waiting */
ldr r9, [r10, #SSP_DATA_OFFSET] /* Load received data */
bx lr /* Exit subroutine */
cs_up:
mov.w r8, #0xff
b cs_write
cs_down:
mov.w r8, #0x0000
cs_write:
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
str.w r8, [r10, #IO_CS_OFFSET]
bx lr
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
bl cs_up /* end the command before returning */
mov r0, r6
bkpt #0x00
.end

125
contrib/loaders/flash/mdr32fx.S
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/***************************************************************************
* Copyright (C) 2011 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* *
* Copyright (C) 2013 by Paul Fertser *
* fercerpav@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.global write
/* Params:
* r0 - flash base (in), status (out)
* r1 - count (32bit)
* r2 - workarea start
* r3 - workarea end
* r4 - target address
* Clobbered:
* r5 - rp
* r6 - wp, tmp
* r7 - current FLASH_CMD
*/
#define FLASH_CMD 0x00
#define FLASH_ADR 0x04
#define FLASH_DI 0x08
#define FLASH_NVSTR (1 << 13)
#define FLASH_PROG (1 << 12)
#define FLASH_MAS1 (1 << 11)
#define FLASH_ERASE (1 << 10)
#define FLASH_SE (1 << 8)
#define FLASH_YE (1 << 7)
#define FLASH_XE (1 << 6)
ldr r7, [r0, #FLASH_CMD]
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
ldr r6, [r5] /* "*target_address++ = *rp++" */
str r4, [r0, #FLASH_ADR]
str r6, [r0, #FLASH_DI]
ldr r6, =(FLASH_XE | FLASH_PROG)
orrs r7, r7, r6
str r7, [r0, #FLASH_CMD]
# wait 5us
movs r6, #5
bl delay
ldr r6, =#FLASH_NVSTR
orrs r7, r7, r6
str r7, [r0, #FLASH_CMD]
# wait 10us
movs r6, #13
bl delay
movs r6, #FLASH_YE
orrs r7, r7, r6
str r7, [r0, #FLASH_CMD]
# wait 40us
movs r6, #61
bl delay
movs r6, #FLASH_YE
bics r7, r7, r6
str r7, [r0, #FLASH_CMD]
ldr r6, =#FLASH_PROG
bics r7, r7, r6
str r7, [r0, #FLASH_CMD]
# wait 5us
movs r6, #5
bl delay
ldr r6, =#(FLASH_XE | FLASH_NVSTR)
bics r7, r7, r6
str r7, [r0, #FLASH_CMD]
adds r5, #4
adds r4, #4
cmp r5, r3 /* wrap rp at end of buffer */
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4] /* store rp */
subs r1, r1, #1 /* decrement word count */
cmp r1, #0
beq exit /* loop if not done */
b wait_fifo
exit:
mov r0, r6 /* return status in r0 */
bkpt #0
/* r6 - in
* for r6 == 1 it'll take:
* 1 (prepare operand) + 4 (bl) + 2 (subs+cmp) + 1 (bne) + 3 (b) ->
* 11 tacts == 1.4us with 8MHz
* every extra iteration will take 5 tacts == 0.6us */
delay:
subs r6, r6, #1
cmp r6, #0
bne delay
bx lr

232
contrib/loaders/flash/mrvlqspi_write.S
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@ -1,232 +0,0 @@
/***************************************************************************
* Copyright (C) 2014 by Mahavir Jain <mjain@marvell.com> *
* *
* Adapted from (contrib/loaders/flash/lpcspifi_write.S): *
* Copyright (C) 2012 by George Harris *
* george@luminairecoffee.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* For compilation:
* arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -c contrib/loaders/flash/mrvlqspi_write.S
* arm-none-eabi-objcopy -O binary mrvlqspi_write.o code.bin
* Copy code.bin into mrvlqspi flash driver
*/
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address (offset from flash base)
* r3 = count (bytes)
* r4 = page size
* r5 = qspi base address
* Clobbered:
* r7 - rp
* r8 - wp, tmp
* r9 - send/receive data
* r10 - current page end address
*/
#define CNTL 0x0
#define CONF 0x4
#define DOUT 0x8
#define DIN 0xc
#define INSTR 0x10
#define ADDR 0x14
#define RDMODE 0x18
#define HDRCNT 0x1c
#define DINCNT 0x20
#define SS_EN (1 << 0)
#define XFER_RDY (1 << 1)
#define RFIFO_EMPTY (1 << 4)
#define WFIFO_EMPTY (1 << 6)
#define WFIFO_FULL (1 << 7)
#define FIFO_FLUSH (1 << 9)
#define RW_EN (1 << 13)
#define XFER_STOP (1 << 14)
#define XFER_START (1 << 15)
#define INS_WRITE_ENABLE 0x06
#define INS_READ_STATUS 0x05
#define INS_PAGE_PROGRAM 0x02
init:
mov.w r10, #0x00
find_next_page_boundary:
add r10, r4 /* Increment to the next page */
cmp r10, r2
/* If we have not reached the next page boundary after the target address, keep going */
bls find_next_page_boundary
write_enable:
/* Flush read/write fifo's */
bl flush_fifo
/* Instruction byte 1 */
movs r8, #0x1
str r8, [r5, #HDRCNT]
/* Set write enable instruction */
movs r8, #INS_WRITE_ENABLE
str r8, [r5, #INSTR]
movs r9, #0x1
bl start_tx
bl stop_tx
page_program:
/* Instruction byte 1, Addr byte 3 */
movs r8, #0x31
str r8, [r5, #HDRCNT]
/* Todo: set addr and data pin to single */
write_address:
mov r8, r2
str r8, [r5, #ADDR]
/* Set page program instruction */
movs r8, #INS_PAGE_PROGRAM
str r8, [r5, #INSTR]
/* Start write transfer */
movs r9, #0x1
bl start_tx
wait_fifo:
ldr r8, [r0] /* read the write pointer */
cmp r8, #0 /* if it's zero, we're gonzo */
beq exit
ldr r7, [r0, #4] /* read the read pointer */
cmp r7, r8 /* wait until they are not equal */
beq wait_fifo
write:
ldrb r9, [r7], #0x01 /* Load one byte from the FIFO, increment the read pointer by 1 */
bl write_data /* send the byte to the flash chip */
cmp r7, r1 /* wrap the read pointer if it is at the end */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store the new read pointer */
subs r3, r3, #1 /* decrement count */
cmp r3, #0 /* Exit if we have written everything */
beq write_wait
add r2, #1 /* Increment flash address by 1 */
cmp r10, r2 /* See if we have reached the end of a page */
bne wait_fifo /* If not, keep writing bytes */
write_wait:
bl stop_tx /* Otherwise, end the command and keep going w/ the next page */
add r10, r4 /* Move up the end-of-page address by the page size*/
check_flash_busy: /* Wait for the flash to finish the previous page write */
/* Flush read/write fifo's */
bl flush_fifo
/* Instruction byte 1 */
movs r8, #0x1
str r8, [r5, #HDRCNT]
/* Continuous data in of status register */
movs r8, #0x0
str r8, [r5, #DINCNT]
/* Set write enable instruction */
movs r8, #INS_READ_STATUS
str r8, [r5, #INSTR]
/* Start read transfer */
movs r9, #0x0
bl start_tx
wait_flash_busy:
bl read_data
and.w r9, r9, #0x1
cmp r9, #0x0
bne.n wait_flash_busy
bl stop_tx
cmp r3, #0
bne.n write_enable /* If it is done, start a new page write */
b exit /* All data written, exit */
write_data: /* Send/receive 1 byte of data over QSPI */
ldr r8, [r5, #CNTL]
lsls r8, r8, #24
bmi.n write_data
str r9, [r5, #DOUT]
bx lr
read_data: /* Read 1 byte of data over QSPI */
ldr r8, [r5, #CNTL]
lsls r8, r8, #27
bmi.n read_data
ldr r9, [r5, #DIN]
bx lr
flush_fifo: /* Flush read write fifos */
ldr r8, [r5, #CONF]
orr.w r8, r8, #FIFO_FLUSH
str r8, [r5, #CONF]
flush_reset:
ldr r8, [r5, #CONF]
lsls r8, r8, #22
bmi.n flush_reset
bx lr
start_tx:
ldr r8, [r5, #CNTL]
orr.w r8, r8, #SS_EN
str r8, [r5, #CNTL]
xfer_rdy:
ldr r8, [r5, #CNTL]
lsls r8, r8, #30
bpl.n xfer_rdy
ldr r8, [r5, #CONF]
bfi r8, r9, #13, #1
orr.w r8, r8, #XFER_START
str r8, [r5, #CONF]
bx lr
stop_tx:
ldr r8, [r5, #CNTL]
lsls r8, r8, #30
bpl.n stop_tx
wfifo_wait:
ldr r8, [r5, #CNTL]
lsls r8, r8, #25
bpl.n wfifo_wait
ldr r8, [r5, #CONF]
orr.w r8, r8, #XFER_STOP
str r8, [r5, #CONF]
xfer_start:
ldr r8, [r5, #CONF]
lsls r8, r8, #16
bmi.n xfer_start
ss_disable:
# Disable SS_EN
ldr r8, [r5, #CNTL]
bic.w r8, r8, #SS_EN
str r8, [r5, #CNTL]
wait:
ldr r8, [r5, #CNTL]
lsls r8, r8, #30
bpl.n wait
bx lr
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
mov r0, r6
bkpt #0x00
.end

132
contrib/loaders/flash/pic32mx.s
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@ -1,132 +0,0 @@
/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arch m4k
.set noreorder
.set noat
/* params:
* $a0 src adr - ram + result
* $a1 dest adr - flash
* $a2 count (32bit words)
* vars
*
* temps:
* $t0, $t1, $t2, $t3, $t4, $t5
* $s0, $s1, $s3, $s4, $s5
*/
.type main, @function
.global main
.ent main
main:
/* setup constants */
lui $t0, 0xaa99
ori $t0, 0x6655 /* NVMKEY1 */
lui $t1, 0x5566
ori $t1, 0x99AA /* NVMKEY2 */
lui $t2, 0xBF80
ori $t2, 0xF400 /* NVMCON */
ori $t3, $zero, 0x4003 /* NVMCON row write cmd */
ori $t4, $zero, 0x8000 /* NVMCON start cmd */
write_row:
/* can we perform a row write: 128 32bit words */
sltiu $s3, $a2, 128
bne $s3, $zero, write_word
ori $t5, $zero, 0x4000 /* NVMCON clear cmd */
/* perform row write 512 bytes */
sw $a1, 32($t2) /* set NVMADDR with dest addr - real addr */
sw $a0, 64($t2) /* set NVMSRCADDR with src addr - real addr */
bal progflash
addiu $a0, $a0, 512
addiu $a1, $a1, 512
beq $zero, $zero, write_row
addiu $a2, $a2, -128
write_word:
/* write 32bit words */
lui $s5, 0xa000
ori $s5, 0x0000
or $a0, $a0, $s5 /* convert to virtual addr */
beq $zero, $zero, next_word
ori $t3, $zero, 0x4001 /* NVMCON word write cmd */
prog_word:
lw $s4, 0($a0) /* load data - from virtual addr */
sw $s4, 48($t2) /* set NVMDATA with data */
sw $a1, 32($t2) /* set NVMADDR with dest addr - real addr */
bal progflash
addiu $a0, $a0, 4
addiu $a1, $a1, 4
addiu $a2, $a2, -1
next_word:
bne $a2, $zero, prog_word
nop
done:
beq $zero, $zero, exit
addiu $a0, $zero, 0
error:
/* save result to $a0 */
addiu $a0, $s1, 0
exit:
sdbbp
.end main
.type progflash, @function
.global progflash
.ent progflash
progflash:
sw $t3, 0($t2) /* set NVMWREN */
sw $t0, 16($t2) /* write NVMKEY1 */
sw $t1, 16($t2) /* write NVMKEY2 */
sw $t4, 8($t2) /* start operation */
waitflash:
lw $s0, 0($t2)
and $s0, $s0, $t4
bne $s0, $zero, waitflash
nop
/* following is to comply with errata #34
* 500ns delay required */
nop
nop
nop
nop
/* check for errors */
lw $s1, 0($t2)
andi $s1, $zero, 0x3000
bne $s1, $zero, error
sw $t5, 4($t2) /* clear NVMWREN */
jr $ra
nop
.end progflash

81
contrib/loaders/flash/sim3x.s
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@ -1,81 +0,0 @@
/***************************************************************************
* Copyright (C) 2014 by Ladislav Bábel *
* ladababel@seznam.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
***************************************************************************/
#define INITIAL_UNLOCK 0x5A
#define MULTIPLE_UNLOCK 0xF2
#define FLASHCTRL_KEY 0x4002E0C0
#define FLASHCTRL_CONFIG 0x4002E000
#define FLASHCTRL_WRADDR 0x4002E0A0
#define FLASHCTRL_WRDATA 0x4002E0B0
#define BUSYF 0x00100000
/* Write the initial unlock value to KEY (0xA5) */
movs r6, #INITIAL_UNLOCK
str r6, [r0, #FLASHCTRL_KEY]
/* Write the multiple unlock value to KEY (0xF2) */
movs r6, #MULTIPLE_UNLOCK
str r6, [r0, #FLASHCTRL_KEY]
wait_fifo:
ldr r6, [r2, #0]
cmp r6, #0
beq exit
ldr r5, [r2, #4]
cmp r5, r6
beq wait_fifo
/* wait for BUSYF flag */
wait_busy1:
ldr r6, [r0, #FLASHCTRL_CONFIG]
tst r6, #BUSYF
bne wait_busy1
/* Write the destination address to WRADDR */
str r4, [r0, #FLASHCTRL_WRADDR]
/* Write the data half-word to WRDATA in right-justified format */
ldrh r6, [r5]
str r6, [r0, #FLASHCTRL_WRDATA]
adds r5, #2
adds r4, #2
/* wrap rp at end of buffer */
cmp r5, r3
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4]
subs r1, r1, #1
cmp r1, #0
beq exit
b wait_fifo
exit:
movs r6, #MULTIPLE_LOCK
str r6, [r0, #FLASHCTRL_KEY]
/* wait for BUSYF flag */
wait_busy2:
ldr r6, [r0, #FLASHCTRL_CONFIG]
tst r6, #BUSYF
bne wait_busy2
bkpt #0

78
contrib/loaders/flash/stellaris.s
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@ -1,78 +0,0 @@
/***************************************************************************
* Copyright (C) 2006 by Magnus Lundin *
* lundin@mlu.mine.nu *
* *
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = workarea start
* r1 = workarea end
* r2 = target address
* r3 = count (32bit words)
*
* Clobbered:
* r4 = pFLASH_CTRL_BASE
* r5 = FLASHWRITECMD
* r7 - rp
* r8 - wp, tmp
*/
write:
ldr r4, pFLASH_CTRL_BASE
ldr r5, FLASHWRITECMD
wait_fifo:
ldr r8, [r0, #0] /* read wp */
cmp r8, #0 /* abort if wp == 0 */
beq exit
ldr r7, [r0, #4] /* read rp */
cmp r7, r8 /* wait until rp != wp */
beq wait_fifo
mainloop:
str r2, [r4, #0] /* FMA - write address */
add r2, r2, #4 /* increment target address */
ldr r8, [r7], #4
str r8, [r4, #4] /* FMD - write data */
str r5, [r4, #8] /* FMC - enable write */
busy:
ldr r8, [r4, #8]
tst r8, #1
bne busy
cmp r7, r1 /* wrap rp at end of buffer */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store rp */
subs r3, r3, #1 /* decrement word count */
cbz r3, exit /* loop if not done */
b wait_fifo
exit:
bkpt #0
pFLASH_CTRL_BASE: .word 0x400FD000
FLASHWRITECMD: .word 0xA4420001

76
contrib/loaders/flash/stm32f1x.S
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@ -1,76 +0,0 @@
/***************************************************************************
* Copyright (C) 2011 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.global write
/* Params:
* r0 - flash base (in), status (out)
* r1 - count (halfword-16bit)
* r2 - workarea start
* r3 - workarea end
* r4 - target address
* Clobbered:
* r5 - rp
* r6 - wp, tmp
* r7 - tmp
*/
#define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register from flash reg base */
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
ldrh r6, [r5] /* "*target_address++ = *rp++" */
strh r6, [r4]
adds r5, #2
adds r4, #2
busy:
ldr r6, [r0, #STM32_FLASH_SR_OFFSET] /* wait until BSY flag is reset */
movs r7, #1
tst r6, r7
bne busy
movs r7, #0x14 /* check the error bits */
tst r6, r7
bne error
cmp r5, r3 /* wrap rp at end of buffer */
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4] /* store rp */
subs r1, r1, #1 /* decrement halfword count */
cmp r1, #0
beq exit /* loop if not done */
b wait_fifo
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0

81
contrib/loaders/flash/stm32f2x.S
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@ -1,81 +0,0 @@
/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2011 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address
* r3 = count (16bit words)
* r4 = flash base
*
* Clobbered:
* r6 - temp
* r7 - rp
* r8 - wp, tmp
*/
#define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register in FLASH struct */
#define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register in FLASH struct */
wait_fifo:
ldr r8, [r0, #0] /* read wp */
cmp r8, #0 /* abort if wp == 0 */
beq exit
ldr r7, [r0, #4] /* read rp */
cmp r7, r8 /* wait until rp != wp */
beq wait_fifo
ldr r6, STM32_PROG16
str r6, [r4, #STM32_FLASH_CR_OFFSET]
ldrh r6, [r7], #0x02 /* read one half-word from src, increment ptr */
strh r6, [r2], #0x02 /* write one half-word from src, increment ptr */
dsb
busy:
ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
tst r6, #0x10000 /* BSY (bit16) == 1 => operation in progress */
bne busy /* wait more... */
tst r6, #0xf0 /* PGSERR | PGPERR | PGAERR | WRPERR */
bne error /* fail... */
cmp r7, r1 /* wrap rp at end of buffer */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store rp */
subs r3, r3, #1 /* decrement halfword count */
cbz r3, exit /* loop if not done */
b wait_fifo
error:
movs r1, #0
str r1, [r0, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0x00
STM32_PROG16: .word 0x101 /* PG | PSIZE_16*/

100
contrib/loaders/flash/stm32l4x.S
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@ -1,100 +0,0 @@
/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2011 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2015 Uwe Bonnes *
* bon@elektron.ikp.physik.tu-darmstadt.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m4
.thumb
.thumb_func
/* To assemble:
* arm-none-eabi-gcc -c stm32l4x.S
*
* To disassemble:
* arm-none-eabi-objdump -o stm32l4x.o
*
* To generate binary file:
* arm-none-eabi-objcopy -O binary stm32l4x.o stm32l4_flash_write_code.bin
*
* To generate include file:
* xxd -i stm32l4_flash_write_code.bin
*/
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address
* r3 = count (64bit words)
* r4 = flash base
*
* Clobbered:
* r5 - rp
* r6/7 - temp (64-bit)
* r8 - wp, tmp
*/
#define STM32_FLASH_CR_OFFSET 0x14 /* offset of CR register in FLASH struct */
#define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */
wait_fifo:
ldr r8, [r0, #0] /* read wp */
cmp r8, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r0, #4] /* read rp */
subs r6, r8, r5 /* number of bytes available for read in r6*/
itt mi /* if wrapped around*/
addmi r6, r1 /* add size of buffer */
submi r6, r0
cmp r6, #8 /* wait until 8 bytes are available */
bcc wait_fifo
ldr r6, STM32_PROG
str r6, [r4, #STM32_FLASH_CR_OFFSET]
ldrd r6, [r5], #0x08 /* read one word from src, increment ptr */
strd r6, [r2], #0x08 /* write one word to dst, increment ptr */
dsb
busy:
ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
tst r6, #0x10000 /* BSY (bit16) == 1 => operation in progress */
bne busy /* wait more... */
tst r6, #0xfa /* PGSERR | PGPERR | PGAERR | WRPERR | PROGERR*/
bne error /* fail... */
cmp r5, r1 /* wrap rp at end of buffer */
it cs
addcs r5, r0, #8 /* skip loader args */
str r5, [r0, #4] /* store rp */
subs r3, r3, #1 /* decrement dword count */
cbz r3, exit /* loop if not done */
b wait_fifo
error:
movs r1, #0
str r1, [r0, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0x00
STM32_PROG: .word 0x1 /* PG */

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