From faa6123e36a4a6a7a1a4c8190a37ae5bfbe183bd Mon Sep 17 00:00:00 2001
From: Palmer Dabbelt <palmer@dabbelt.com>
Date: Thu, 25 May 2017 13:10:28 -0700
Subject: [PATCH] Invalidate the register cache on step, resume, reset

I thought OpenOCD did this, but it looks like that doesn't happen when
runningi in RTOS mode.  With this I can get to the end of most of the
RTOS tests, but they SIGINT instead of exiting.
---
 src/target/riscv/riscv.c | 11 +++++++++++
 src/target/riscv/riscv.h |  3 +++
 2 files changed, 14 insertions(+)

diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index c083636e6..f89df6ebf 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -914,6 +914,7 @@ int riscv_resume_all_harts(struct target *target)
 		riscv_resume_one_hart(target, riscv_current_hartid(target));
 	}
 
+	riscv_invalidate_register_cache(target);
 	return ERROR_OK;
 }
 
@@ -941,6 +942,7 @@ int riscv_reset_all_harts(struct target *target)
 		riscv_reset_one_hart(target, riscv_current_hartid(target));
 	}
 
+	riscv_invalidate_register_cache(target);
 	return ERROR_OK;
 }
 
@@ -973,8 +975,10 @@ int riscv_step_rtos_hart(struct target *target)
 	LOG_DEBUG("stepping hart %d", hartid);
 
 	assert(riscv_is_halted(target));
+	riscv_invalidate_register_cache(target);
 	r->on_step(target);
 	r->step_current_hart(target);
+	riscv_invalidate_register_cache(target);
 	r->on_halt(target);
 	assert(riscv_is_halted(target));
 	return ERROR_OK;
@@ -1019,6 +1023,13 @@ void riscv_set_current_hartid(struct target *target, int hartid)
 	} else
 		LOG_DEBUG("Initializing registers: xlen=%d", riscv_xlen(target));
 
+	riscv_invalidate_register_cache(target);
+}
+
+void riscv_invalidate_register_cache(struct target *target)
+{
+	RISCV_INFO(r);
+
 	/* Update the register list's widths. */
 	register_cache_invalidate(target->reg_cache);
 	for (size_t i = 0; i < GDB_REGNO_COUNT; ++i) {
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h
index a51456f28..7b27b3538 100644
--- a/src/target/riscv/riscv.h
+++ b/src/target/riscv/riscv.h
@@ -211,4 +211,7 @@ void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t
 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a);
 int riscv_dmi_write_u64_bits(struct target *target);
 
+/* Invalidates the register cache. */
+void riscv_invalidate_register_cache(struct target *target);
+
 #endif