riscv-compliance: Fix OpenOCD lint checks
This commit is contained in:
Megan Wachs
parent
bc32aaafa4
commit
fa99b8e3b1
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@ -2934,7 +2934,8 @@ void riscv013_clear_abstract_error(struct target *target)
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dmi_write(target, DMI_ABSTRACTCS, abstractcs & DMI_ABSTRACTCS_CMDERR);
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}
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#define COMPLIANCE_TEST(b, message) { \
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#define COMPLIANCE_TEST(b, message) \
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{ \
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int pass = 0; \
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if (b) { \
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pass = 1; \
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@ -2945,7 +2946,8 @@ void riscv013_clear_abstract_error(struct target *target)
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total_tests++; \
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}
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int riscv013_test_compliance(struct target *target) {
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int riscv013_test_compliance(struct target *target)
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{
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LOG_INFO("Testing Compliance against RISC-V Debug Spec v0.13");
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if (!riscv_rtos_enabled(target)) {
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@ -2966,14 +2968,15 @@ int riscv013_test_compliance(struct target *target) {
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dmcontrol = set_field(dmcontrol_orig, hartsel_mask(target), RISCV_MAX_HARTS-1);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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COMPLIANCE_TEST(get_field(dmcontrol, hartsel_mask(target)) == (RISCV_MAX_HARTS-1), "DMCONTROL.hartsel should hold all the harts allowed by HARTSELLEN.");
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COMPLIANCE_TEST(get_field(dmcontrol, hartsel_mask(target)) == (RISCV_MAX_HARTS-1),
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"DMCONTROL.hartsel should hold all the harts allowed by HARTSELLEN.");
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dmcontrol = set_field(dmcontrol_orig, hartsel_mask(target), 0);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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COMPLIANCE_TEST(get_field(dmcontrol, hartsel_mask(target)) == 0, "DMCONTROL.hartsel should hold Hart ID 0");
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// hartreset
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/* hartreset */
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dmcontrol = set_field(dmcontrol_orig, DMI_DMCONTROL_HARTRESET, 1);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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@ -2981,9 +2984,10 @@ int riscv013_test_compliance(struct target *target) {
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dmcontrol = set_field(dmcontrol_orig, DMI_DMCONTROL_HARTRESET, 1);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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COMPLIANCE_TEST(((testvar == 0) || (get_field(dmcontrol, DMI_DMCONTROL_HARTRESET)) == 0), "DMCONTROL.hartreset can be 0 or RW.");
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COMPLIANCE_TEST(((testvar == 0) || (get_field(dmcontrol, DMI_DMCONTROL_HARTRESET)) == 0),
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"DMCONTROL.hartreset can be 0 or RW.");
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// hasel
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/* hasel */
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dmcontrol = set_field(dmcontrol_orig, DMI_DMCONTROL_HASEL, 1);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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@ -2991,13 +2995,14 @@ int riscv013_test_compliance(struct target *target) {
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dmcontrol = set_field(dmcontrol_orig, DMI_DMCONTROL_HASEL, 1);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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COMPLIANCE_TEST(((testvar == 0) || (get_field(dmcontrol, DMI_DMCONTROL_HASEL)) == 0), "DMCONTROL.hasel can be 0 or RW.");
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//TODO: test that hamask registers exist if hasel does.
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COMPLIANCE_TEST(((testvar == 0) || (get_field(dmcontrol, DMI_DMCONTROL_HASEL)) == 0),
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"DMCONTROL.hasel can be 0 or RW.");
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/* TODO: test that hamask registers exist if hasel does. */
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// haltreq
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/* haltreq */
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riscv_halt_all_harts(target);
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// Writing haltreq should not cause any problems for a halted hart, but we
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// should be able to read and write it.
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/* Writing haltreq should not cause any problems for a halted hart, but we
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should be able to read and write it. */
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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dmcontrol |= DMI_DMCONTROL_HALTREQ;
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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@ -3012,18 +3017,19 @@ int riscv013_test_compliance(struct target *target) {
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dmi_read(target, &dmstatus_read, DMI_DMSTATUS);
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COMPLIANCE_TEST(dmstatus_read == dmstatus, "DMSTATUS is R/O");
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// resumereq. This will resume the hart but this test is destructive anyway.
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/* resumereq. This will resume the hart but this test is destructive anyway. */
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dmcontrol &= ~DMI_DMCONTROL_HALTREQ;
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dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_RESUMEREQ, 1);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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COMPLIANCE_TEST(get_field(dmcontrol, DMI_DMCONTROL_RESUMEREQ) == 1, "DMCONTROL.resumereq should be R/W");
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COMPLIANCE_TEST(get_field(dmcontrol, DMI_DMCONTROL_RESUMEREQ) == 1,
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"DMCONTROL.resumereq should be R/W");
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do {
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dmi_read(target, &dmstatus, DMI_DMSTATUS);
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} while (get_field(dmstatus, DMI_DMSTATUS_ALLRESUMEACK) == 0);
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// Halt the hart again because the target isn't aware that we resumed it.
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/* Halt the hart again because the target isn't aware that we resumed it. */
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dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_RESUMEREQ, 0);
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dmcontrol |= DMI_DMCONTROL_HALTREQ;
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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@ -3032,10 +3038,10 @@ int riscv013_test_compliance(struct target *target) {
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} while ((dmstatus & DMI_DMSTATUS_ALLHALTED) == 0);
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dmcontrol &= ~DMI_DMCONTROL_HALTREQ;
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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// Not clear that this read is required according to the spec.
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/* Not clear that this read is required according to the spec. */
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dmi_read(target, &dmstatus, DMI_DMSTATUS);
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// HARTINFO: Read-Only. This is per-hart, so need to adjust hartsel.
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/* HARTINFO: Read-Only. This is per-hart, so need to adjust hartsel. */
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for (int hartsel = 0; hartsel < riscv_count_harts(target); hartsel++) {
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riscv_set_current_hartid(target, hartsel);
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@ -3047,47 +3053,53 @@ int riscv013_test_compliance(struct target *target) {
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uint32_t nscratch = get_field(hartinfo, DMI_HARTINFO_NSCRATCH);
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for (unsigned int d = 0; d < nscratch; d++) {
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//TODO: DSCRATCH CSRs should be 64-bit on 64-bit systems.
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/* TODO: DSCRATCH CSRs should be 64-bit on 64-bit systems. */
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riscv_reg_t testval;
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for (testval = 0x0011223300112233; testval != 0xDEAD ; testval = testval == 0x0011223300112233 ? ~testval : 0xDEAD ) {
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COMPLIANCE_TEST(register_write_direct(target, GDB_REGNO_S0, testval) == ERROR_OK, "Need to be able to write S0 in order to test DSCRATCH.");
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for (testval = 0x0011223300112233;
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testval != 0xDEAD;
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testval = testval == 0x0011223300112233 ? ~testval : 0xDEAD) {
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COMPLIANCE_TEST(register_write_direct(target, GDB_REGNO_S0, testval) == ERROR_OK,
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"Need to be able to write S0 in order to test DSCRATCH.");
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struct riscv_program program32;
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riscv_program_init(&program32, target);
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riscv_program_csrw(&program32, GDB_REGNO_S0, GDB_REGNO_DSCRATCH + d);
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riscv_program_csrr(&program32, GDB_REGNO_S1, GDB_REGNO_DSCRATCH + d);
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riscv_program_fence(&program32);
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riscv_program_ebreak(&program32);
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COMPLIANCE_TEST(riscv_program_exec(&program32, target) == ERROR_OK, "Accessing DSCRATCH with program buffer should succeed.");
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COMPLIANCE_TEST(register_read_direct(target, &value, GDB_REGNO_S1) == ERROR_OK, "Need to be able to read S1 in order to test DSCRATCH.");
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if (riscv_xlen(target) > 32) {
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COMPLIANCE_TEST(value == testval, "All DSCRATCH registers in HARTINFO must be R/W.");
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} else {
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COMPLIANCE_TEST(value == (testval & 0xFFFFFFFF), "All DSCRATCH registers in HARTINFO must be R/W.");
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COMPLIANCE_TEST(riscv_program_exec(&program32, target) == ERROR_OK,
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"Accessing DSCRATCH with program buffer should succeed.");
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COMPLIANCE_TEST(register_read_direct(target, &value, GDB_REGNO_S1) == ERROR_OK,
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"Need to be able to read S1 in order to test DSCRATCH.");
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if (riscv_xlen(target) > 32)
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COMPLIANCE_TEST(value == testval,
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"All DSCRATCH registers in HARTINFO must be R/W.");
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else
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COMPLIANCE_TEST(value == (testval & 0xFFFFFFFF),
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"All DSCRATCH registers in HARTINFO must be R/W.");
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}
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}
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}
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// TODO: dataaccess
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/* TODO: dataaccess */
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if (get_field(hartinfo, DMI_HARTINFO_DATAACCESS)) {
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// TODO: Shadowed in memory map.
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// TODO: datasize
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// TODO: dataaddr
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/* TODO: Shadowed in memory map. */
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/* TODO: datasize */
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/* TODO: dataaddr */
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} else {
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// TODO: Shadowed in CSRs.
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// TODO: datasize
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// TODO: dataaddr
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/* TODO: Shadowed in CSRs. */
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/* TODO: datasize */
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/* TODO: dataaddr */
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}
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}
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// HALTSUM -- TODO: More than 32 harts
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// TODO: HALTSUM2, HALTSUM3
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/* HALTSUM -- TODO: More than 32 harts */
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/* TODO: HALTSUM2, HALTSUM3 */
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uint32_t expected_haltsum0 = 0;
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for (int i = 0; i < riscv_count_harts(target); i +=32){
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for (int i = 0; i < riscv_count_harts(target); i += 32)
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expected_haltsum0 |= (1 << (i / 32));
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}
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dmi_read(target, &testvar_read, DMI_HALTSUM0);
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COMPLIANCE_TEST(testvar_read == expected_haltsum0, "HALTSUM0 should report summary of 32 halted harts");
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COMPLIANCE_TEST(testvar_read == expected_haltsum0,
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"HALTSUM0 should report summary of 32 halted harts");
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dmi_write(target, DMI_HALTSUM0, 0xffffffff);
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dmi_read(target, &testvar_read, DMI_HALTSUM0);
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@ -3098,12 +3110,15 @@ int riscv013_test_compliance(struct target *target) {
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COMPLIANCE_TEST(testvar_read == expected_haltsum0, "HALTSUM0 should be R/O");
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for (int i = 0; i < 32/*TODO: riscv_count_harts(target)*/; i += 32) {
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//TODO: Set hartsel for i > 32 harts.
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/* TODO: Set hartsel for i > 32 harts. */
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dmi_read(target, &testvar_read, DMI_HALTSUM1);
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uint32_t haltsum1_expected = (((i + 1) * 32) <= riscv_count_harts(target)) ? 0xFFFFFFFFU : ((1U << (riscv_count_harts(target) % 32)) - 1);
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COMPLIANCE_TEST(testvar_read == haltsum1_expected, "HALTSUM1 should report summary of 1024 halted harts");
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uint32_t haltsum1_expected = (((i + 1) * 32) <= riscv_count_harts(target)) ?
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0xFFFFFFFFU :
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((1U << (riscv_count_harts(target) % 32)) - 1);
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COMPLIANCE_TEST(testvar_read == haltsum1_expected,
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"HALTSUM1 should report summary of 1024 halted harts");
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// Just have to check this once
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/* Just have to check this once */
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if (i == 0) {
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dmi_write(target, DMI_HALTSUM1, 0xffffffff);
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dmi_read(target, &testvar_read, DMI_HALTSUM1);
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@ -3115,50 +3130,54 @@ int riscv013_test_compliance(struct target *target) {
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}
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}
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// TODO: HAWINDOWSEL
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/* TODO: HAWINDOWSEL */
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// TODO: HAWINDOW
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/* TODO: HAWINDOW */
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// ABSTRACTCS
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/* ABSTRACTCS */
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uint32_t abstractcs;
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dmi_read(target, &abstractcs, DMI_ABSTRACTCS);
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// Check that all reported Data Words are really R/W
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/* Check that all reported Data Words are really R/W */
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for (int invert = 0; invert < 2; invert++) {
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for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT); i++) {
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testvar = (i + 1) * 0x11111111;
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if (invert) {testvar = ~testvar;}
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if (invert)
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testvar = ~testvar;
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dmi_write(target, DMI_DATA0 + i, testvar);
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}
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for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT); i++) {
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testvar = (i + 1) * 0x11111111;
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if (invert) {testvar = ~testvar;}
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if (invert)
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testvar = ~testvar;
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dmi_read(target, &testvar_read, DMI_DATA0 + i);
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COMPLIANCE_TEST(testvar_read == testvar, "All reported DATA words must be R/W");
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}
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}
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// Check that all reported ProgBuf words are really R/W
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/*Check that all reported ProgBuf words are really R/W */
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for (int invert = 0; invert < 2; invert++) {
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for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE); i++) {
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testvar = (i + 1) * 0x11111111;
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if (invert) {testvar = ~testvar;}
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if (invert)
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testvar = ~testvar;
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dmi_write(target, DMI_PROGBUF0 + i, testvar);
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}
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for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE); i++) {
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testvar = (i + 1) * 0x11111111;
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if (invert) {testvar = ~testvar;}
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if (invert)
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testvar = ~testvar;
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dmi_read(target, &testvar_read, DMI_PROGBUF0 + i);
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COMPLIANCE_TEST(testvar_read == testvar, "All reported PROGBUF words must be R/W");
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}
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}
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// TODO: Cause and clear all error types
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/* TODO: Cause and clear all error types */
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// COMMAND
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// TODO: Unclear from the spec whether all these bits need to truly be R/W.
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// But at any rate, this is not legal and should cause an error.
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/* COMMAND
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TODO: Unclear from the spec whether all these bits need to truly be R/W.
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But at any rate, this is not legal and should cause an error. */
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dmi_write(target, DMI_COMMAND, 0xAAAAAAAA);
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dmi_read(target, &testvar_read, DMI_COMMAND);
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COMPLIANCE_TEST(testvar_read == 0xAAAAAAAA, "COMMAND register should be R/W");
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@ -3174,7 +3193,7 @@ int riscv013_test_compliance(struct target *target) {
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"Illegal COMMAND should result in UNSUPPORTED");
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dmi_write(target, DMI_ABSTRACTCS, DMI_ABSTRACTCS_CMDERR);
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// Basic Abstract Commands
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/* Basic Abstract Commands */
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uint32_t command = 0;
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uint32_t busy;
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command = set_field(command, AC_ACCESS_REGISTER_SIZE, riscv_xlen(target) > 32 ? 3 : 2);
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@ -3183,20 +3202,19 @@ int riscv013_test_compliance(struct target *target) {
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command = set_field(command, AC_ACCESS_REGISTER_REGNO, 0x1000 + GDB_REGNO_ZERO + i);
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command = set_field(command, AC_ACCESS_REGISTER_WRITE, 1);
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dmi_write(target, DMI_DATA0, i);
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if (riscv_xlen(target) > 32) {
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if (riscv_xlen(target) > 32)
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dmi_write(target, DMI_DATA0 + 1, i + 1);
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}
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dmi_write(target, DMI_COMMAND, command);
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do {
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dmi_read(target, &testvar_read, DMI_ABSTRACTCS);
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busy = get_field(testvar_read, DMI_ABSTRACTCS_BUSY);
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} while (busy);
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dmi_read(target, &testvar_read, DMI_ABSTRACTCS);
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COMPLIANCE_TEST(get_field(testvar_read, DMI_ABSTRACTCS_CMDERR) == 0, "GPR Writes should be supported.");
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COMPLIANCE_TEST(get_field(testvar_read, DMI_ABSTRACTCS_CMDERR) == 0,
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"GPR Writes should be supported.");
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dmi_write(target, DMI_DATA0, 0xDEADBEEF);
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if (riscv_xlen(target) > 32) {
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if (riscv_xlen(target) > 32)
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dmi_write(target, DMI_DATA0 + 1, 0xDEADBEEF);
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}
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command = set_field(command, AC_ACCESS_REGISTER_WRITE, 0);
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dmi_write(target, DMI_COMMAND, command);
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do {
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@ -3204,30 +3222,32 @@ int riscv013_test_compliance(struct target *target) {
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busy = get_field(testvar_read, DMI_ABSTRACTCS_BUSY);
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} while (busy);
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dmi_read(target, &testvar_read, DMI_ABSTRACTCS);
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COMPLIANCE_TEST(get_field(testvar_read, DMI_ABSTRACTCS_CMDERR) == 0, "GPR Reads should be supported.");
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COMPLIANCE_TEST(get_field(testvar_read, DMI_ABSTRACTCS_CMDERR) == 0,
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"GPR Reads should be supported.");
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dmi_read(target, &testvar_read, DMI_DATA0);
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COMPLIANCE_TEST(testvar_read == i, "GPR Reads and writes should be supported.");
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if (riscv_xlen(target) > 32) {
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dmi_read(target, &testvar_read, DMI_DATA0 + 1);
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COMPLIANCE_TEST(testvar_read == (i + 1), "GPR Reads and writes should be supported.");
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COMPLIANCE_TEST(testvar_read == (i + 1),
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"GPR Reads and writes should be supported.");
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}
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}
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// ABSTRACTAUTO
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// See which bits are actually writable
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/* ABSTRACTAUTO
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See which bits are actually writable */
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dmi_write(target, DMI_ABSTRACTAUTO, 0xFFFFFFFF);
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uint32_t abstractauto;
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dmi_read(target, &abstractauto, DMI_ABSTRACTAUTO);
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dmi_write(target, DMI_ABSTRACTAUTO, 0x0);
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if (abstractauto > 0) {
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testvar = 0;
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// TODO: This mechanism only works when you have a reasonable sized progbuf, which is not
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// a true compliance requirement.
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/* TODO: This mechanism only works when you have a reasonable sized progbuf, which is not
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a true compliance requirement. */
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uint32_t result = riscv_set_register(target, GDB_REGNO_S0, 0);
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COMPLIANCE_TEST(result == ERROR_OK, "Need to be able to write S0 to test ABSTRACTAUTO");
|
||||
struct riscv_program program;
|
||||
riscv_program_init(&program, target);
|
||||
// Also testing that WFI() is a NOP during debug mode.
|
||||
/* Also testing that WFI() is a NOP during debug mode. */
|
||||
riscv_program_insert(&program, wfi());
|
||||
riscv_program_addi(&program, GDB_REGNO_S0, GDB_REGNO_S0, 1);
|
||||
riscv_program_ebreak(&program);
|
||||
|
|
@ -3245,7 +3265,8 @@ int riscv013_test_compliance(struct target *target) {
|
|||
busy = get_field(testvar_read, DMI_ABSTRACTCS_BUSY);
|
||||
} while (busy);
|
||||
if (autoexec_data & (1 << i)) {
|
||||
COMPLIANCE_TEST(i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT), "AUTOEXEC may be writable up to DATACOUNT bits.");
|
||||
COMPLIANCE_TEST(i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT),
|
||||
"AUTOEXEC may be writable up to DATACOUNT bits.");
|
||||
testvar++;
|
||||
}
|
||||
}
|
||||
|
|
@ -3256,7 +3277,8 @@ int riscv013_test_compliance(struct target *target) {
|
|||
busy = get_field(testvar_read, DMI_ABSTRACTCS_BUSY);
|
||||
} while (busy);
|
||||
if (autoexec_progbuf & (1 << i)) {
|
||||
COMPLIANCE_TEST(i < get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE), "AUTOEXEC may be writable up to PROGBUFSIZE bits.");
|
||||
COMPLIANCE_TEST(i < get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE),
|
||||
"AUTOEXEC may be writable up to PROGBUFSIZE bits.");
|
||||
testvar++;
|
||||
}
|
||||
}
|
||||
|
|
@ -3268,20 +3290,21 @@ int riscv013_test_compliance(struct target *target) {
|
|||
"ABSTRACTAUTO should cause COMMAND to run the expected number of times.");
|
||||
}
|
||||
|
||||
// Single-Step each hart.
|
||||
/* Single-Step each hart. */
|
||||
for (int hartsel = 0; hartsel < riscv_count_harts(target); hartsel++) {
|
||||
riscv_set_current_hartid(target, hartsel);
|
||||
riscv013_on_step(target);
|
||||
riscv013_step_current_hart(target);
|
||||
COMPLIANCE_TEST(riscv_halt_reason(target, hartsel) == RISCV_HALT_SINGLESTEP, "Single Step should result in SINGLESTEP");
|
||||
COMPLIANCE_TEST(riscv_halt_reason(target, hartsel) == RISCV_HALT_SINGLESTEP,
|
||||
"Single Step should result in SINGLESTEP");
|
||||
}
|
||||
|
||||
// Core Register Tests
|
||||
/* Core Register Tests */
|
||||
uint64_t bogus_dpc = 0xdeadbeef;
|
||||
for (int hartsel = 0; hartsel < riscv_count_harts(target); hartsel++) {
|
||||
riscv_set_current_hartid(target, hartsel);
|
||||
|
||||
// DCSR Tests
|
||||
/* DCSR Tests */
|
||||
riscv_set_register(target, GDB_REGNO_DCSR, 0x0);
|
||||
riscv_get_register(target, &value, GDB_REGNO_DCSR);
|
||||
COMPLIANCE_TEST(value != 0, "Not all bits in DCSR are writable by Debugger");
|
||||
|
|
@ -3289,33 +3312,34 @@ int riscv013_test_compliance(struct target *target) {
|
|||
riscv_get_register(target, &value, GDB_REGNO_DCSR);
|
||||
COMPLIANCE_TEST(value != 0, "At least some bits in DCSR must be 1");
|
||||
|
||||
// DPC. Note that DPC is sign-extended.
|
||||
/* DPC. Note that DPC is sign-extended. */
|
||||
riscv_reg_t dpcmask = 0xFFFFFFFCUL;
|
||||
riscv_reg_t dpc;
|
||||
|
||||
if (riscv_xlen(target) > 32) {
|
||||
if (riscv_xlen(target) > 32)
|
||||
dpcmask |= (0xFFFFFFFFULL << 32);
|
||||
}
|
||||
if (riscv_supports_extension(target, riscv_current_hartid(target), 'C')){
|
||||
|
||||
if (riscv_supports_extension(target, riscv_current_hartid(target), 'C'))
|
||||
dpcmask |= 0x2;
|
||||
}
|
||||
|
||||
riscv_set_register(target, GDB_REGNO_DPC, dpcmask);
|
||||
riscv_get_register(target, &dpc, GDB_REGNO_DPC);
|
||||
COMPLIANCE_TEST(dpcmask == dpc, "DPC must be sign-extended to XLEN and writable to all-1s (except the least significant bits)");
|
||||
COMPLIANCE_TEST(dpcmask == dpc,
|
||||
"DPC must be sign-extended to XLEN and writable to all-1s (except the least significant bits)");
|
||||
riscv_set_register(target, GDB_REGNO_DPC, 0);
|
||||
riscv_get_register(target, &dpc, GDB_REGNO_DPC);
|
||||
COMPLIANCE_TEST(dpc == 0, "DPC must be writable to 0.");
|
||||
if (hartsel == 0) {bogus_dpc = dpc;} // For a later test step
|
||||
if (hartsel == 0)
|
||||
bogus_dpc = dpc; /* For a later test step */
|
||||
}
|
||||
|
||||
//NDMRESET
|
||||
// NDMRESET
|
||||
// Asserting non-debug module reset should not reset Debug Module state.
|
||||
// But it should reset Hart State, e.g. DPC should get a different value.
|
||||
// Also make sure that DCSR reports cause of 'HALT' even though previously we single-stepped.
|
||||
/* NDMRESET
|
||||
Asserting non-debug module reset should not reset Debug Module state.
|
||||
But it should reset Hart State, e.g. DPC should get a different value.
|
||||
Also make sure that DCSR reports cause of 'HALT' even though previously we single-stepped.
|
||||
*/
|
||||
|
||||
// Write some registers. They should not be impacted by ndmreset.
|
||||
/* Write some registers. They should not be impacted by ndmreset. */
|
||||
dmi_write(target, DMI_COMMAND, 0xFFFFFFFF);
|
||||
|
||||
for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE); i++) {
|
||||
|
|
@ -3331,7 +3355,7 @@ int riscv013_test_compliance(struct target *target) {
|
|||
dmi_write(target, DMI_ABSTRACTAUTO, 0xFFFFFFFF);
|
||||
dmi_read(target, &abstractauto, DMI_ABSTRACTAUTO);
|
||||
|
||||
// Pulse reset.
|
||||
/* Pulse reset. */
|
||||
|
||||
target->reset_halt = true;
|
||||
dmi_read(target, &dmcontrol, DMI_DMCONTROL);
|
||||
|
|
@ -3339,15 +3363,16 @@ int riscv013_test_compliance(struct target *target) {
|
|||
assert_reset(target);
|
||||
deassert_reset(target);
|
||||
|
||||
// Verify that most stuff is not affected by ndmreset.
|
||||
/* Verify that most stuff is not affected by ndmreset. */
|
||||
dmi_read(target, &testvar_read, DMI_COMMAND);
|
||||
COMPLIANCE_TEST(testvar_read == 0xFFFFFFFF, "NDMRESET should not affect DMI_COMMAND");
|
||||
dmi_read(target, &testvar_read, DMI_ABSTRACTCS);
|
||||
COMPLIANCE_TEST(get_field(testvar_read, DMI_ABSTRACTCS_CMDERR) == CMDERR_NOT_SUPPORTED, "NDMRESET should not affect DMI_ABSTRACTCS");
|
||||
COMPLIANCE_TEST(get_field(testvar_read, DMI_ABSTRACTCS_CMDERR) == CMDERR_NOT_SUPPORTED,
|
||||
"NDMRESET should not affect DMI_ABSTRACTCS");
|
||||
dmi_read(target, &testvar_read, DMI_ABSTRACTAUTO);
|
||||
COMPLIANCE_TEST(testvar_read == abstractauto, "NDMRESET should not affect DMI_ABSTRACTAUTO");
|
||||
|
||||
// Clean up to avoid future test failures
|
||||
/* Clean up to avoid future test failures */
|
||||
dmi_write(target, DMI_ABSTRACTCS, DMI_ABSTRACTCS_CMDERR);
|
||||
dmi_write(target, DMI_ABSTRACTAUTO, 0);
|
||||
|
||||
|
|
@ -3363,17 +3388,19 @@ int riscv013_test_compliance(struct target *target) {
|
|||
COMPLIANCE_TEST(testvar_read == testvar, "DATA words must not be affected by NDMRESET");
|
||||
}
|
||||
|
||||
// verify that DPC *is* affected by ndmreset. Since we don't know what it *should* be,
|
||||
// just verify that at least it's not the bogus value anymore.
|
||||
/* Verify that DPC *is* affected by ndmreset. Since we don't know what it *should* be,
|
||||
just verify that at least it's not the bogus value anymore. */
|
||||
|
||||
COMPLIANCE_TEST(bogus_dpc != 0xdeadbeef, "BOGUS DPC should have been set somehow (bug in compliance test)");
|
||||
riscv_get_register(target, &value, GDB_REGNO_DPC);
|
||||
COMPLIANCE_TEST(bogus_dpc != value, "NDMRESET should move DPC to reset value.");
|
||||
|
||||
COMPLIANCE_TEST(riscv_halt_reason(target, 0) == RISCV_HALT_INTERRUPT, "After NDMRESET halt, DCSR should report cause of halt");
|
||||
COMPLIANCE_TEST(riscv_halt_reason(target, 0) == RISCV_HALT_INTERRUPT,
|
||||
"After NDMRESET halt, DCSR should report cause of halt");
|
||||
|
||||
// DMACTIVE -- deasserting DMACTIVE should reset all the above values.
|
||||
/* DMACTIVE -- deasserting DMACTIVE should reset all the above values. */
|
||||
|
||||
// Toggle dmactive
|
||||
/* Toggle dmactive */
|
||||
dmi_write(target, DMI_DMCONTROL, 0);
|
||||
dmi_write(target, DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE);
|
||||
dmi_read(target, &testvar_read, DMI_COMMAND);
|
||||
|
|
@ -3395,21 +3422,22 @@ int riscv013_test_compliance(struct target *target) {
|
|||
COMPLIANCE_TEST(testvar_read == 0, "DATA words should reset to 0");
|
||||
}
|
||||
|
||||
//TODO:
|
||||
// DCSR.cause priorities
|
||||
// DCSR.stoptime/stopcycle
|
||||
// DCSR.stepie
|
||||
// DCSR.ebreak
|
||||
// DCSR.prv
|
||||
/*
|
||||
* TODO:
|
||||
* DCSR.cause priorities
|
||||
* DCSR.stoptime/stopcycle
|
||||
* DCSR.stepie
|
||||
* DCSR.ebreak
|
||||
* DCSR.prv
|
||||
*/
|
||||
|
||||
/* Halt every hart for any follow-up tests*/
|
||||
riscv_halt_all_harts(target);
|
||||
|
||||
LOG_INFO("PASSED %d of %d TESTS\n", passed_tests, total_tests);
|
||||
|
||||
if (total_tests == passed_tests) {
|
||||
if (total_tests == passed_tests)
|
||||
return ERROR_OK;
|
||||
} else {
|
||||
else
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue