diff --git a/Changelog_Nuclei.md b/Changelog_Nuclei.md index 87cece7c9..23871c597 100644 --- a/Changelog_Nuclei.md +++ b/Changelog_Nuclei.md @@ -8,6 +8,27 @@ If the tool version and documentation version not match, please take care. ## 2024.12 +* improvement of ci and doc +* replace vslide1down_vx to read/write vx register +* support live watch feature +* organize nuclei commands into nuclei_riscv.c +* add nuclei cti command group +* update nuclei etrace command group +* optimise nuclei cpuinfo command + +* add new nuclei customized csr + | new csr addr | new csr name | + | ------ | ------ | + | 0x1a4~0x1af | smpuaddr4~15 | + | 0x1c0~0x1ef | smpuaddr16~63 | +* rename nuclei customized csr + | old name | new name | + | ------ | ------ | + | spmpcfg0~3 | smpucfg0~3 | + | spmpaddr0~15 | smpuaddr0~15 | + | mfp16mode | mmisc_ctl1 | + | mecc_ctrl | mecc_ctl | + | mstack_ctrl | mstack_ctl | * changes are based on [riscv/riscv-openocd](https://github.com/riscv-collab/riscv-openocd/commit/f9a12927) ## 2024.06 diff --git a/README.md b/README.md new file mode 100644 index 000000000..f0a463615 --- /dev/null +++ b/README.md @@ -0,0 +1,15 @@ +# Notice + +If you are looking for how to build Nuclei OpenOCD, +please follow this [guidance](https://github.com/riscv-mcu/openocd-xpack/blob/xpack_nuclei_next/README-BUILD-Nuclei.md) + +About how to use openocd, please check http://openocd.org/documentation/ + +[![Build Nuclei OpenOCD](https://github.com/riscv-mcu/riscv-openocd/workflows/Build%20Nuclei%20OpenOCD/badge.svg)](https://github.com/riscv-mcu/riscv-openocd/actions) + +- `nuclei-master` - the updated content, used during builds and releases +- `nuclei-develop` - the updated content, used during development + +Since we are always merging changes from upstream, forced update to these two branches +might be happened in future, please take care. + diff --git a/doc/openocd.texi b/doc/openocd.texi index 06b4f05fc..0342b7d32 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -79,6 +79,7 @@ Documentation License''. * JTAG Commands:: JTAG Commands * Boundary Scan Commands:: Boundary Scan Commands * Utility Commands:: Utility Commands +* Nuclei Commands:: Nuclei Commands * GDB and OpenOCD:: Using GDB and OpenOCD * Tcl Scripting API:: Tcl Scripting API * FAQ:: Frequently Asked Questions @@ -6386,6 +6387,17 @@ flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME @end example @end deffn +@deffn {Flash Driver} {nuspi} +@cindex Nuclei SPI +@cindex nuspi + +Nuclei's SPI controller, used in Nuclei RISC-V fpga evaluation board and other boards. + +@example +flash bank $_FLASHNAME nuspi 0x20000000 0 0 0 $_TARGETNAME +@end example +@end deffn + @subsection Internal Flash (Microcontrollers) @deffn {Flash Driver} {aduc702x} @@ -12612,6 +12624,169 @@ For quickstart instructions run: openocd -f tools/firmware-recovery.tcl -c firmware_help @end example +@node Nuclei Commands +@chapter Nuclei Commands +@cindex Nuclei Commands + +The commands here apply only to Nuclei series CPUs. + +@section Show CPU Info +@cindex Show CPU Info + +Usually we don't know what instruction sets a CPU supports, +what functional components it contains, and the various configurations +of the components. The only way to get the desired information is to +read the corresponding CSR registers and then do the math. It would +be a pain in the ass to do this for every function point that needs +to be known. This command is designed to solve this problem by +automatically reading the CSRs and doing the math, and then formatting the output. + +This command should be executed after the @command{init} command. + +@deffn {Command} {nuclei cpuinfo} +Displays some information about the currently used CPU. +@end deffn + +@section Etrace Commands +@cindex Etrace Commands + +Some Nuclei cpus are equipped with trace support, which permits +examination of the instruction activity. Trace activity is controlled +through an ``Embedded Trace``(Etrace) Module on the core's scan chains. +The following commands are for etrace. + +This command should be executed after the @command{init} command. + +@deffn {Command} {nuclei etrace config} atb2axi-config-addr buffer-addr buffer-size wrap +Configure each parameter needed for etrace. +Command options: +@itemize @bullet +@item @option{atb2axi-config-addr} The address of the atb2axi controller. +@item @option{buffer-addr} The base address of etrace buffer. +@item @option{buffer-size} The bytes size of the etrace buffer. +@item @option{wrap} [0|1] Whether trace data is automatically looped back for overwriting. +@end itemize +@end deffn + +@deffn {Command} {nuclei etrace enable} +Enable the etrace switch within the CPU. +@end deffn + +@deffn {Command} {nuclei etrace disable} +Disable the etrace switch within the CPU. +@end deffn + +@deffn {Command} {nuclei etrace start} +Start etrace data collection. +@end deffn + +@deffn {Command} {nuclei etrace stop} +Stop etrace data collection. +@end deffn + +@deffn {Command} {nuclei etrace dump} filename +dump etrace data to the specified file. +@end deffn + +@deffn {Command} {nuclei etrace clear} +clear etrace register status and flags. +@end deffn + +@deffn {Command} {nuclei etrace info} +display etrace some info. +@end deffn + +@section Extended Commands +@cindex Extended Commands + +Nuclei extends the functionality of some existing commands, as described below. + +@deffn {Command} {ftdi nscan1_mode} on|off +Enable or disable Nuclei CJTAG mode. Usage is the same as @command{ftdi oscan1_mode}. +@end deffn + +@deffn {Command} {flash bank} name driver base size chip_width bus_width target [driver_options] +Nuclei extends this command with two drivers, nuspi and custom. +Use can refer to the @command{flash bank} command. +@end deffn + +@itemize @bullet +@item @option{driver_options} ... + +For nuspi, [driver_options] has two options, the final command +format looks like this: +@example +flash bank name nuspi base size chip_width bus_width target \ +[spi_base] [simulation] +@end example + +For custom, [driver_options] has three options, the final command +format looks like this: +@example +flash bank name custom base size chip_width bus_width target \ +spi_base loader_path [simulation] [sectorsize=] +@end example + +@end itemize + +Here are some examples for nuspi: +@example +# if spi_base is not specified then spi_base is 0x10014000. +flash bank $FLASHNAME nuspi 0x20000000 0 0 0 $TARGETNAME + +# Without the simulation parameter, the flash operation will have +# a timeout, the value of which is automatically calculated according +# to the size of the operation data volume. +flash bank $FLASHNAME nuspi 0x20000000 0 0 0 $TARGETNAME 0x10180000 + +# If the simulation parameter is present, the flash operation will +# no longer time out. +flash bank $FLASHNAME nuspi 0x20000000 0 0 0 $TARGETNAME 0x10180000 \ +simulation +@end example + +Here are some examples for custom: +@example +# Without the simulation parameter, the flash operation will have a +# timeout, the value of which is automatically calculated according +# to the size of the operation data volume. +flash bank $FLASHNAME custom 0x20000000 0 0 0 $TARGETNAME 0x10180000 \ +/home/admin/flashloader.bin + +# If the simulation parameter is present, the flash operation will no +# longer time out. if the sectorsize parameter is not specified, +# then sectorsize is 0x10000. +flash bank $FLASHNAME custom 0x20000000 0 0 0 $TARGETNAME 0x10180000 \ +/home/admin/flashloader.bin simulation + +flash bank $FLASHNAME custom 0x20000000 0 0 0 $TARGETNAME 0x10180000 \ +/home/admin/flashloader.bin sectorsize=0x1000 + +flash bank $FLASHNAME custom 0x20000000 0 0 0 $TARGETNAME 0x10180000 \ +/home/admin/flashloader.bin simulation sectorsize=0x1000 + +flash bank $FLASHNAME nuspi 0x20000000 0 0 0 $TARGETNAME 0x10180000 \ +/home/admin/flashloader.bin sectorsize=0x1000 simulation +@end example + +This flashloader.bin is compiled and generated through the openocd-flashloader project, +the open source address is https://github.com/riscv-mcu/openflashloader. + +@deffn {Command} {init} resethalt +Nuclei extends the init command with the resethalt parameter. +Usage is the same as @command{init}. +@end deffn + +In practice, usually encountered due to software problems caused by the CPU stuck, +then the debugger will not be connected to the development board, only to the +development board power off. If your code is running in flash, powering down +the board will not solve the problem. resethalt is designed to solve this problem. + +Here are some examples: +@example +init resethalt +@end example + @node GDB and OpenOCD @chapter GDB and OpenOCD @cindex GDB