Transform 'u16' to 'uint16_t'
- Replace '\([^_]\)u16' with '\1uint16_t'. - Replace '^u16' with 'uint16_t'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2277 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
zwelch
parent
c18947b947
commit
f876d5e9c7
|
|
@ -57,7 +57,7 @@ static int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
|||
static u32 at91sam7_get_flash_status(target_t *target, int bank_number);
|
||||
static void at91sam7_set_flash_mode(flash_bank_t *bank, int mode);
|
||||
static u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
|
||||
static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, u16 pagen);
|
||||
static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16_t pagen);
|
||||
static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
|
||||
flash_driver_t at91sam7_flash =
|
||||
|
|
@ -274,7 +274,7 @@ static u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeo
|
|||
}
|
||||
|
||||
/* Send one command to the AT91SAM flash controller */
|
||||
static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, u16 pagen)
|
||||
static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16_t pagen)
|
||||
{
|
||||
u32 fcr;
|
||||
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
|
||||
|
|
@ -309,14 +309,14 @@ static int at91sam7_read_part_info(struct flash_bank_s *bank)
|
|||
at91sam7_flash_bank_t *at91sam7_info;
|
||||
target_t *target = t_bank->target;
|
||||
|
||||
u16 bnk, sec;
|
||||
u16 arch;
|
||||
uint16_t bnk, sec;
|
||||
uint16_t arch;
|
||||
u32 cidr;
|
||||
uint8_t banks_num = 0;
|
||||
u16 num_nvmbits = 0;
|
||||
u16 sectors_num = 0;
|
||||
u16 pages_per_sector = 0;
|
||||
u16 page_size = 0;
|
||||
uint16_t num_nvmbits = 0;
|
||||
uint16_t sectors_num = 0;
|
||||
uint16_t pages_per_sector = 0;
|
||||
uint16_t page_size = 0;
|
||||
u32 ext_freq;
|
||||
u32 bank_size;
|
||||
u32 base_address = 0;
|
||||
|
|
@ -621,12 +621,12 @@ static int at91sam7_read_part_info(struct flash_bank_s *bank)
|
|||
static int at91sam7_erase_check(struct flash_bank_s *bank)
|
||||
{
|
||||
target_t *target = bank->target;
|
||||
u16 retval;
|
||||
uint16_t retval;
|
||||
u32 blank;
|
||||
u16 fast_check;
|
||||
uint16_t fast_check;
|
||||
uint8_t *buffer;
|
||||
u16 nSector;
|
||||
u16 nByte;
|
||||
uint16_t nSector;
|
||||
uint16_t nByte;
|
||||
|
||||
if (bank->target->state != TARGET_HALTED)
|
||||
{
|
||||
|
|
@ -759,9 +759,9 @@ static int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *
|
|||
int banks_num;
|
||||
int num_sectors;
|
||||
|
||||
u16 pages_per_sector;
|
||||
u16 page_size;
|
||||
u16 num_nvmbits;
|
||||
uint16_t pages_per_sector;
|
||||
uint16_t page_size;
|
||||
uint16_t num_nvmbits;
|
||||
|
||||
char *target_name;
|
||||
|
||||
|
|
|
|||
|
|
@ -29,30 +29,30 @@ typedef struct at91sam7_flash_bank_s
|
|||
{
|
||||
/* chip id register */
|
||||
u32 cidr;
|
||||
u16 cidr_ext;
|
||||
u16 cidr_nvptyp;
|
||||
u16 cidr_arch;
|
||||
u16 cidr_sramsiz;
|
||||
u16 cidr_nvpsiz;
|
||||
u16 cidr_nvpsiz2;
|
||||
u16 cidr_eproc;
|
||||
u16 cidr_version;
|
||||
uint16_t cidr_ext;
|
||||
uint16_t cidr_nvptyp;
|
||||
uint16_t cidr_arch;
|
||||
uint16_t cidr_sramsiz;
|
||||
uint16_t cidr_nvpsiz;
|
||||
uint16_t cidr_nvpsiz2;
|
||||
uint16_t cidr_eproc;
|
||||
uint16_t cidr_version;
|
||||
char *target_name;
|
||||
|
||||
/* flash auto-detection */
|
||||
uint8_t flash_autodetection;
|
||||
|
||||
/* flash geometry */
|
||||
u16 pages_per_sector;
|
||||
u16 pagesize;
|
||||
u16 pages_in_lockregion;
|
||||
uint16_t pages_per_sector;
|
||||
uint16_t pagesize;
|
||||
uint16_t pages_in_lockregion;
|
||||
|
||||
/* nv memory bits */
|
||||
u16 num_lockbits_on;
|
||||
u16 lockbits;
|
||||
u16 num_nvmbits;
|
||||
u16 num_nvmbits_on;
|
||||
u16 nvmbits;
|
||||
uint16_t num_lockbits_on;
|
||||
uint16_t lockbits;
|
||||
uint16_t num_nvmbits;
|
||||
uint16_t num_nvmbits_on;
|
||||
uint16_t nvmbits;
|
||||
uint8_t securitybit;
|
||||
|
||||
/* 0: not init
|
||||
|
|
|
|||
|
|
@ -76,8 +76,8 @@ extern int mcu_write_ir(jtag_tap_t *tap, uint8_t *ir_in, uint8_t *ir_out, int ir
|
|||
extern int mcu_write_dr(jtag_tap_t *tap, uint8_t *ir_in, uint8_t *ir_out, int dr_len, int rti);
|
||||
extern int mcu_write_ir_u8(jtag_tap_t *tap, uint8_t *ir_in, uint8_t ir_out, int ir_len, int rti);
|
||||
extern int mcu_write_dr_u8(jtag_tap_t *tap, uint8_t *ir_in, uint8_t ir_out, int dr_len, int rti);
|
||||
extern int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti);
|
||||
extern int mcu_write_dr_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int dr_len, int rti);
|
||||
extern int mcu_write_ir_u16(jtag_tap_t *tap, uint16_t *ir_in, uint16_t ir_out, int ir_len, int rti);
|
||||
extern int mcu_write_dr_u16(jtag_tap_t *tap, uint16_t *ir_in, uint16_t ir_out, int dr_len, int rti);
|
||||
extern int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti);
|
||||
extern int mcu_write_dr_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int dr_len, int rti);
|
||||
extern int mcu_execute_queue(void);
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
typedef struct avrf_type_s
|
||||
{
|
||||
char name[15];
|
||||
u16 chip_id;
|
||||
uint16_t chip_id;
|
||||
int flash_page_size;
|
||||
int flash_page_num;
|
||||
int eeprom_page_size;
|
||||
|
|
|
|||
|
|
@ -203,7 +203,7 @@ static uint8_t cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
|
|||
}
|
||||
}
|
||||
|
||||
static u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
|
||||
static uint16_t cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
|
||||
{
|
||||
target_t *target = bank->target;
|
||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||
|
|
@ -979,8 +979,8 @@ static void cfi_add_byte(struct flash_bank_s *bank, uint8_t *word, uint8_t byte)
|
|||
/* NOTE:
|
||||
* The data to flash must not be changed in endian! We write a bytestrem in
|
||||
* target byte order already. Only the control and status byte lane of the flash
|
||||
* WSM is interpreted by the CPU in different ways, when read a u16 or u32
|
||||
* word (data seems to be in the upper or lower byte lane for u16 accesses).
|
||||
* WSM is interpreted by the CPU in different ways, when read a uint16_t or u32
|
||||
* word (data seems to be in the upper or lower byte lane for uint16_t accesses).
|
||||
*/
|
||||
|
||||
#if 0
|
||||
|
|
|
|||
|
|
@ -34,16 +34,16 @@ typedef struct cfi_flash_bank_s
|
|||
int not_cfi;
|
||||
int probed;
|
||||
|
||||
u16 manufacturer;
|
||||
u16 device_id;
|
||||
uint16_t manufacturer;
|
||||
uint16_t device_id;
|
||||
|
||||
char qry[3];
|
||||
|
||||
/* identification string */
|
||||
u16 pri_id;
|
||||
u16 pri_addr;
|
||||
u16 alt_id;
|
||||
u16 alt_addr;
|
||||
uint16_t pri_id;
|
||||
uint16_t pri_addr;
|
||||
uint16_t alt_id;
|
||||
uint16_t alt_addr;
|
||||
|
||||
/* device-system interface */
|
||||
uint8_t vcc_min;
|
||||
|
|
@ -63,8 +63,8 @@ typedef struct cfi_flash_bank_s
|
|||
|
||||
/* flash geometry */
|
||||
u32 dev_size;
|
||||
u16 interface_desc;
|
||||
u16 max_buf_write_size;
|
||||
uint16_t interface_desc;
|
||||
uint16_t max_buf_write_size;
|
||||
uint8_t num_erase_regions;
|
||||
u32 *erase_region_info;
|
||||
|
||||
|
|
@ -83,11 +83,11 @@ typedef struct cfi_intel_pri_ext_s
|
|||
uint8_t minor_version;
|
||||
u32 feature_support;
|
||||
uint8_t suspend_cmd_support;
|
||||
u16 blk_status_reg_mask;
|
||||
uint16_t blk_status_reg_mask;
|
||||
uint8_t vcc_optimal;
|
||||
uint8_t vpp_optimal;
|
||||
uint8_t num_protection_fields;
|
||||
u16 prot_reg_addr;
|
||||
uint16_t prot_reg_addr;
|
||||
uint8_t fact_prot_reg_size;
|
||||
uint8_t user_prot_reg_size;
|
||||
uint8_t extra[0];
|
||||
|
|
@ -144,8 +144,8 @@ typedef struct cfi_unlock_addresses_s
|
|||
|
||||
typedef struct cfi_fixup_s
|
||||
{
|
||||
u16 mfr;
|
||||
u16 id;
|
||||
uint16_t mfr;
|
||||
uint16_t id;
|
||||
void (*fixup)(flash_bank_t *flash, void *param);
|
||||
void *param;
|
||||
} cfi_fixup_t;
|
||||
|
|
|
|||
|
|
@ -157,7 +157,7 @@ static int davinci_address(struct nand_device_s *nand, uint8_t address)
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int davinci_write_data(struct nand_device_s *nand, u16 data)
|
||||
static int davinci_write_data(struct nand_device_s *nand, uint16_t data)
|
||||
{
|
||||
struct davinci_nand *info = nand->controller_priv;
|
||||
target_t *target = info->target;
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ static int lpc3180_init(struct nand_device_s *device);
|
|||
static int lpc3180_reset(struct nand_device_s *device);
|
||||
static int lpc3180_command(struct nand_device_s *device, uint8_t command);
|
||||
static int lpc3180_address(struct nand_device_s *device, uint8_t address);
|
||||
static int lpc3180_write_data(struct nand_device_s *device, u16 data);
|
||||
static int lpc3180_write_data(struct nand_device_s *device, uint16_t data);
|
||||
static int lpc3180_read_data(struct nand_device_s *device, void *data);
|
||||
static int lpc3180_write_page(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
|
||||
static int lpc3180_read_page(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
|
||||
|
|
@ -410,7 +410,7 @@ static int lpc3180_address(struct nand_device_s *device, uint8_t address)
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int lpc3180_write_data(struct nand_device_s *device, u16 data)
|
||||
static int lpc3180_write_data(struct nand_device_s *device, uint16_t data)
|
||||
{
|
||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||
target_t *target = lpc3180_info->target;
|
||||
|
|
@ -466,7 +466,7 @@ static int lpc3180_read_data(struct nand_device_s *device, void *data)
|
|||
}
|
||||
else if (device->bus_width == 16)
|
||||
{
|
||||
u16 *data16 = data;
|
||||
uint16_t *data16 = data;
|
||||
target_read_u16(target, 0x200b0000, data16);
|
||||
}
|
||||
else
|
||||
|
|
@ -489,7 +489,7 @@ static int lpc3180_read_data(struct nand_device_s *device, void *data)
|
|||
}
|
||||
else if (device->bus_width == 16)
|
||||
{
|
||||
u16 *data16 = data;
|
||||
uint16_t *data16 = data;
|
||||
*data16 = data32 & 0xffff;
|
||||
}
|
||||
else
|
||||
|
|
|
|||
|
|
@ -956,8 +956,8 @@ static double mg_calc_pll(double XIN, mg_pll_t *p_pll_val)
|
|||
|
||||
static int mg_verify_interface(void)
|
||||
{
|
||||
u16 buff[MG_MFLASH_SECTOR_SIZE >> 1];
|
||||
u16 i, j;
|
||||
uint16_t buff[MG_MFLASH_SECTOR_SIZE >> 1];
|
||||
uint16_t i, j;
|
||||
u32 address = mflash_bank->base + MG_BUFFER_OFFSET;
|
||||
target_t *target = mflash_bank->target;
|
||||
int ret;
|
||||
|
|
@ -1174,7 +1174,7 @@ static int mg_set_pll(mg_pll_t *pll)
|
|||
memset(buff, 0xff, 512);
|
||||
/* PLL Lock cycle and Feedback 9bit Divider */
|
||||
memcpy(buff, &pll->lock_cyc, sizeof(u32));
|
||||
memcpy(buff + 4, &pll->feedback_div, sizeof(u16));
|
||||
memcpy(buff + 4, &pll->feedback_div, sizeof(uint16_t));
|
||||
buff[6] = pll->input_div; /* PLL Input 5bit Divider */
|
||||
buff[7] = pll->output_div; /* PLL Output Divider */
|
||||
|
||||
|
|
@ -1306,7 +1306,7 @@ static int mg_bank_cmd(struct command_context_s *cmd_ctx, char *cmd, char **args
|
|||
mflash_bank->base = strtoul(args[1], NULL, 0);
|
||||
mflash_bank->rst_pin.num = strtoul(args[2], &str, 0);
|
||||
if (*str)
|
||||
mflash_bank->rst_pin.port[0] = (u16)tolower(str[0]);
|
||||
mflash_bank->rst_pin.port[0] = (uint16_t)tolower(str[0]);
|
||||
|
||||
mflash_bank->target = target;
|
||||
|
||||
|
|
|
|||
|
|
@ -384,7 +384,7 @@ int nand_read_status(struct nand_device_s *device, uint8_t *status)
|
|||
/* read status */
|
||||
if (device->device->options & NAND_BUSWIDTH_16)
|
||||
{
|
||||
u16 data;
|
||||
uint16_t data;
|
||||
device->controller->read_data(device, &data);
|
||||
*status = data & 0xff;
|
||||
}
|
||||
|
|
@ -403,7 +403,7 @@ static int nand_poll_ready(struct nand_device_s *device, int timeout)
|
|||
device->controller->command(device, NAND_CMD_STATUS);
|
||||
do {
|
||||
if (device->device->options & NAND_BUSWIDTH_16) {
|
||||
u16 data;
|
||||
uint16_t data;
|
||||
device->controller->read_data(device, &data);
|
||||
status = data & 0xff;
|
||||
} else {
|
||||
|
|
@ -464,7 +464,7 @@ int nand_probe(struct nand_device_s *device)
|
|||
}
|
||||
else
|
||||
{
|
||||
u16 data_buf;
|
||||
uint16_t data_buf;
|
||||
device->controller->read_data(device, &data_buf);
|
||||
manufacturer_id = data_buf & 0xff;
|
||||
device->controller->read_data(device, &data_buf);
|
||||
|
|
@ -524,7 +524,7 @@ int nand_probe(struct nand_device_s *device)
|
|||
}
|
||||
else
|
||||
{
|
||||
u16 data_buf;
|
||||
uint16_t data_buf;
|
||||
|
||||
device->controller->read_data(device, &data_buf);
|
||||
id_buff[3] = data_buf;
|
||||
|
|
@ -996,7 +996,7 @@ int nand_write_page_raw(struct nand_device_s *device, u32 page, uint8_t *data, u
|
|||
{
|
||||
if (device->device->options & NAND_BUSWIDTH_16)
|
||||
{
|
||||
u16 data_buf = le_to_h_u16(data);
|
||||
uint16_t data_buf = le_to_h_u16(data);
|
||||
device->controller->write_data(device, data_buf);
|
||||
data += 2;
|
||||
i += 2;
|
||||
|
|
@ -1021,7 +1021,7 @@ int nand_write_page_raw(struct nand_device_s *device, u32 page, uint8_t *data, u
|
|||
{
|
||||
if (device->device->options & NAND_BUSWIDTH_16)
|
||||
{
|
||||
u16 oob_buf = le_to_h_u16(data);
|
||||
uint16_t oob_buf = le_to_h_u16(data);
|
||||
device->controller->write_data(device, oob_buf);
|
||||
oob += 2;
|
||||
i += 2;
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ typedef struct nand_flash_controller_s
|
|||
int (*reset)(struct nand_device_s *device);
|
||||
int (*command)(struct nand_device_s *device, uint8_t command);
|
||||
int (*address)(struct nand_device_s *device, uint8_t address);
|
||||
int (*write_data)(struct nand_device_s *device, u16 data);
|
||||
int (*write_data)(struct nand_device_s *device, uint16_t data);
|
||||
int (*read_data)(struct nand_device_s *device, void *data);
|
||||
int (*write_block_data)(struct nand_device_s *device, uint8_t *data, int size);
|
||||
int (*read_block_data)(struct nand_device_s *device, uint8_t *data, int size);
|
||||
|
|
|
|||
|
|
@ -137,7 +137,7 @@ int nand_calculate_ecc_kw(struct nand_device_s *device, const uint8_t *data, uin
|
|||
d = data[i];
|
||||
|
||||
if (r7) {
|
||||
u16 *t = gf_exp + gf_log[r7];
|
||||
uint16_t *t = gf_exp + gf_log[r7];
|
||||
|
||||
r7 = r6 ^ t[0x21c];
|
||||
r6 = r5 ^ t[0x181];
|
||||
|
|
|
|||
|
|
@ -24,12 +24,12 @@
|
|||
|
||||
typedef struct non_cfi_s
|
||||
{
|
||||
u16 mfr;
|
||||
u16 id;
|
||||
u16 pri_id;
|
||||
uint16_t mfr;
|
||||
uint16_t id;
|
||||
uint16_t pri_id;
|
||||
u32 dev_size;
|
||||
u16 interface_desc;
|
||||
u16 max_buf_write_size;
|
||||
uint16_t interface_desc;
|
||||
uint16_t max_buf_write_size;
|
||||
uint8_t num_erase_regions;
|
||||
u32 erase_region_info[6];
|
||||
uint8_t status_poll_mask;
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@ static int orion_nand_read(struct nand_device_s *device, void *data)
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int orion_nand_write(struct nand_device_s *device, u16 data)
|
||||
static int orion_nand_write(struct nand_device_s *device, uint16_t data)
|
||||
{
|
||||
orion_nand_controller_t *hw = device->controller_priv;
|
||||
target_t *target = hw->target;
|
||||
|
|
|
|||
|
|
@ -260,7 +260,7 @@ static int pic32mx_protect(struct flash_bank_s *bank, int set, int first, int la
|
|||
pic32mx_flash_bank_t *pic32mx_info = NULL;
|
||||
target_t *target = bank->target;
|
||||
#if 0
|
||||
u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
|
||||
uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
|
||||
int i, reg, bit;
|
||||
int status;
|
||||
u32 protection;
|
||||
|
|
@ -285,10 +285,10 @@ static int pic32mx_protect(struct flash_bank_s *bank, int set, int first, int la
|
|||
* high density - each bit refers to a 2bank protection */
|
||||
target_read_u32(target, PIC32MX_FLASH_WRPR, &protection);
|
||||
|
||||
prot_reg[0] = (u16)protection;
|
||||
prot_reg[1] = (u16)(protection >> 8);
|
||||
prot_reg[2] = (u16)(protection >> 16);
|
||||
prot_reg[3] = (u16)(protection >> 24);
|
||||
prot_reg[0] = (uint16_t)protection;
|
||||
prot_reg[1] = (uint16_t)(protection >> 8);
|
||||
prot_reg[2] = (uint16_t)(protection >> 16);
|
||||
prot_reg[3] = (uint16_t)(protection >> 24);
|
||||
|
||||
if (pic32mx_info->ppage_size == 2)
|
||||
{
|
||||
|
|
@ -596,7 +596,7 @@ static int pic32mx_probe(struct flash_bank_s *bank)
|
|||
mips32_common_t *mips32 = target->arch_info;
|
||||
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
|
||||
int i;
|
||||
u16 num_pages = 0;
|
||||
uint16_t num_pages = 0;
|
||||
u32 device_id;
|
||||
int page_size;
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
static int s3c2410_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
|
||||
static int s3c2410_init(struct nand_device_s *device);
|
||||
static int s3c2410_read_data(struct nand_device_s *device, void *data);
|
||||
static int s3c2410_write_data(struct nand_device_s *device, u16 data);
|
||||
static int s3c2410_write_data(struct nand_device_s *device, uint16_t data);
|
||||
static int s3c2410_nand_ready(struct nand_device_s *device, int timeout);
|
||||
|
||||
nand_flash_controller_t s3c2410_nand_controller =
|
||||
|
|
@ -86,7 +86,7 @@ static int s3c2410_init(struct nand_device_s *device)
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int s3c2410_write_data(struct nand_device_s *device, u16 data)
|
||||
static int s3c2410_write_data(struct nand_device_s *device, uint16_t data)
|
||||
{
|
||||
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
||||
target_t *target = s3c24xx_info->target;
|
||||
|
|
|
|||
|
|
@ -104,7 +104,7 @@ int s3c24xx_address(struct nand_device_s *device, uint8_t address)
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int s3c24xx_write_data(struct nand_device_s *device, u16 data)
|
||||
int s3c24xx_write_data(struct nand_device_s *device, uint16_t data)
|
||||
{
|
||||
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
||||
target_t *target = s3c24xx_info->target;
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ extern int s3c24xx_register_commands(struct command_context_s *cmd_ctx);
|
|||
extern int s3c24xx_reset(struct nand_device_s *device);
|
||||
extern int s3c24xx_command(struct nand_device_s *device, uint8_t command);
|
||||
extern int s3c24xx_address(struct nand_device_s *device, uint8_t address);
|
||||
extern int s3c24xx_write_data(struct nand_device_s *device, u16 data);
|
||||
extern int s3c24xx_write_data(struct nand_device_s *device, uint16_t data);
|
||||
extern int s3c24xx_read_data(struct nand_device_s *device, void *data);
|
||||
extern int s3c24xx_controller_ready(struct nand_device_s *device, int tout);
|
||||
|
||||
|
|
|
|||
|
|
@ -412,7 +412,7 @@ static u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int time
|
|||
}
|
||||
|
||||
/* Send one command to the flash controller */
|
||||
static int stellaris_flash_command(struct flash_bank_s *bank,uint8_t cmd,u16 pagen)
|
||||
static int stellaris_flash_command(struct flash_bank_s *bank,uint8_t cmd,uint16_t pagen)
|
||||
{
|
||||
u32 fmc;
|
||||
target_t *target = bank->target;
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ typedef struct stellaris_flash_bank_s
|
|||
u32 pages_in_lockregion;
|
||||
|
||||
/* nv memory bits */
|
||||
u16 num_lockbits;
|
||||
uint16_t num_lockbits;
|
||||
u32 lockbits;
|
||||
|
||||
/* main clock status */
|
||||
|
|
|
|||
|
|
@ -140,7 +140,7 @@ static int stm32x_read_options(struct flash_bank_s *bank)
|
|||
/* read current option bytes */
|
||||
target_read_u32(target, STM32_FLASH_OBR, &optiondata);
|
||||
|
||||
stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
|
||||
stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8|((optiondata >> 2) & 0x07);
|
||||
stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
|
||||
|
||||
if (optiondata & (1 << OPT_READOUT))
|
||||
|
|
@ -149,10 +149,10 @@ static int stm32x_read_options(struct flash_bank_s *bank)
|
|||
/* each bit refers to a 4bank protection */
|
||||
target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
|
||||
|
||||
stm32x_info->option_bytes.protection[0] = (u16)optiondata;
|
||||
stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
|
||||
stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
|
||||
stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
|
||||
stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
|
||||
stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
|
||||
stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
|
||||
stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
@ -394,7 +394,7 @@ static int stm32x_protect(struct flash_bank_s *bank, int set, int first, int las
|
|||
{
|
||||
stm32x_flash_bank_t *stm32x_info = NULL;
|
||||
target_t *target = bank->target;
|
||||
u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
|
||||
uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
|
||||
int i, reg, bit;
|
||||
int status;
|
||||
u32 protection;
|
||||
|
|
@ -417,10 +417,10 @@ static int stm32x_protect(struct flash_bank_s *bank, int set, int first, int las
|
|||
* high density - each bit refers to a 2bank protection */
|
||||
target_read_u32(target, STM32_FLASH_WRPR, &protection);
|
||||
|
||||
prot_reg[0] = (u16)protection;
|
||||
prot_reg[1] = (u16)(protection >> 8);
|
||||
prot_reg[2] = (u16)(protection >> 16);
|
||||
prot_reg[3] = (u16)(protection >> 24);
|
||||
prot_reg[0] = (uint16_t)protection;
|
||||
prot_reg[1] = (uint16_t)(protection >> 8);
|
||||
prot_reg[2] = (uint16_t)(protection >> 16);
|
||||
prot_reg[3] = (uint16_t)(protection >> 24);
|
||||
|
||||
if (stm32x_info->ppage_size == 2)
|
||||
{
|
||||
|
|
@ -650,8 +650,8 @@ static int stm32x_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset,
|
|||
|
||||
while (words_remaining > 0)
|
||||
{
|
||||
u16 value;
|
||||
memcpy(&value, buffer + bytes_written, sizeof(u16));
|
||||
uint16_t value;
|
||||
memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
|
||||
|
||||
target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
|
||||
target_write_u16(target, address, value);
|
||||
|
|
@ -676,7 +676,7 @@ static int stm32x_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset,
|
|||
|
||||
if (bytes_remaining)
|
||||
{
|
||||
u16 value = 0xffff;
|
||||
uint16_t value = 0xffff;
|
||||
memcpy(&value, buffer + bytes_written, bytes_remaining);
|
||||
|
||||
target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
|
||||
|
|
@ -706,7 +706,7 @@ static int stm32x_probe(struct flash_bank_s *bank)
|
|||
target_t *target = bank->target;
|
||||
stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
|
||||
int i;
|
||||
u16 num_pages;
|
||||
uint16_t num_pages;
|
||||
u32 device_id;
|
||||
int page_size;
|
||||
|
||||
|
|
@ -1094,7 +1094,7 @@ static int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx
|
|||
flash_bank_t *bank;
|
||||
target_t *target = NULL;
|
||||
stm32x_flash_bank_t *stm32x_info = NULL;
|
||||
u16 optionbyte = 0xF8;
|
||||
uint16_t optionbyte = 0xF8;
|
||||
|
||||
if (argc < 4)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -27,9 +27,9 @@
|
|||
|
||||
typedef struct stm32x_options_s
|
||||
{
|
||||
u16 RDP;
|
||||
u16 user_options;
|
||||
u16 protection[4];
|
||||
uint16_t RDP;
|
||||
uint16_t user_options;
|
||||
uint16_t protection[4];
|
||||
} stm32x_options_t;
|
||||
|
||||
typedef struct stm32x_flash_bank_s
|
||||
|
|
|
|||
|
|
@ -646,8 +646,8 @@ static int str7x_handle_disable_jtag_command(struct command_context_s *cmd_ctx,
|
|||
|
||||
u32 flash_cmd;
|
||||
u32 retval;
|
||||
u16 ProtectionLevel = 0;
|
||||
u16 ProtectionRegs;
|
||||
uint16_t ProtectionLevel = 0;
|
||||
uint16_t ProtectionRegs;
|
||||
|
||||
if (argc < 1)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -183,7 +183,7 @@ static int str9x_protect_check(struct flash_bank_s *bank)
|
|||
int i;
|
||||
u32 adr;
|
||||
u32 status = 0;
|
||||
u16 hstatus = 0;
|
||||
uint16_t hstatus = 0;
|
||||
|
||||
if (bank->target->state != TARGET_HALTED)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -786,11 +786,11 @@ static int tms470_erase_sector(struct flash_bank_s *bank, int sector)
|
|||
* clear status regiser, sent erase command, kickoff erase
|
||||
*/
|
||||
target_write_u16(target, flashAddr, 0x0040);
|
||||
LOG_DEBUG("write *(u16 *)0x%08x=0x0040", flashAddr);
|
||||
LOG_DEBUG("write *(uint16_t *)0x%08x=0x0040", flashAddr);
|
||||
target_write_u16(target, flashAddr, 0x0020);
|
||||
LOG_DEBUG("write *(u16 *)0x%08x=0x0020", flashAddr);
|
||||
LOG_DEBUG("write *(uint16_t *)0x%08x=0x0020", flashAddr);
|
||||
target_write_u16(target, flashAddr, 0xffff);
|
||||
LOG_DEBUG("write *(u16 *)0x%08x=0xffff", flashAddr);
|
||||
LOG_DEBUG("write *(uint16_t *)0x%08x=0xffff", flashAddr);
|
||||
|
||||
/*
|
||||
* Monitor FMMSTAT, busy until clear, then check and other flags for
|
||||
|
|
@ -994,7 +994,7 @@ static int tms470_write(struct flash_bank_s *bank, uint8_t * buffer, u32 offset,
|
|||
for (i = 0; i < count; i += 2)
|
||||
{
|
||||
u32 addr = bank->base + offset + i;
|
||||
u16 word = (((u16) buffer[i]) << 8) | (u16) buffer[i + 1];
|
||||
uint16_t word = (((uint16_t) buffer[i]) << 8) | (uint16_t) buffer[i + 1];
|
||||
|
||||
if (word != 0xffff)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -34,8 +34,8 @@
|
|||
typedef unsigned char uint8_t;
|
||||
#endif
|
||||
|
||||
#ifndef u16
|
||||
typedef unsigned short u16;
|
||||
#ifndef uint16_t
|
||||
typedef unsigned short uint16_t;
|
||||
#endif
|
||||
|
||||
#ifndef u32
|
||||
|
|
@ -93,9 +93,9 @@ static inline u32 le_to_h_u32(const uint8_t* buf)
|
|||
return (u32)(buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24);
|
||||
}
|
||||
|
||||
static inline u16 le_to_h_u16(const uint8_t* buf)
|
||||
static inline uint16_t le_to_h_u16(const uint8_t* buf)
|
||||
{
|
||||
return (u16)(buf[0] | buf[1] << 8);
|
||||
return (uint16_t)(buf[0] | buf[1] << 8);
|
||||
}
|
||||
|
||||
static inline u32 be_to_h_u32(const uint8_t* buf)
|
||||
|
|
@ -103,9 +103,9 @@ static inline u32 be_to_h_u32(const uint8_t* buf)
|
|||
return (u32)(buf[3] | buf[2] << 8 | buf[1] << 16 | buf[0] << 24);
|
||||
}
|
||||
|
||||
static inline u16 be_to_h_u16(const uint8_t* buf)
|
||||
static inline uint16_t be_to_h_u16(const uint8_t* buf)
|
||||
{
|
||||
return (u16)(buf[1] | buf[0] << 8);
|
||||
return (uint16_t)(buf[1] | buf[0] << 8);
|
||||
}
|
||||
|
||||
static inline void h_u32_to_le(uint8_t* buf, int val)
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@
|
|||
#endif
|
||||
|
||||
/* configuration */
|
||||
static u16 amt_jtagaccel_port;
|
||||
static uint16_t amt_jtagaccel_port;
|
||||
|
||||
/* interface variables
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -107,8 +107,8 @@ static unsigned ft2232_max_tck = 6000;
|
|||
|
||||
#define MAX_USB_IDS 8
|
||||
/* vid = pid = 0 marks the end of the list */
|
||||
static u16 ft2232_vid[MAX_USB_IDS + 1] = { 0x0403, 0 };
|
||||
static u16 ft2232_pid[MAX_USB_IDS + 1] = { 0x6010, 0 };
|
||||
static uint16_t ft2232_vid[MAX_USB_IDS + 1] = { 0x0403, 0 };
|
||||
static uint16_t ft2232_pid[MAX_USB_IDS + 1] = { 0x6010, 0 };
|
||||
|
||||
typedef struct ft2232_layout_s
|
||||
{
|
||||
|
|
@ -1780,7 +1780,7 @@ static int ft2232_execute_queue()
|
|||
|
||||
|
||||
#if BUILD_FT2232_FTD2XX == 1
|
||||
static int ft2232_init_ftd2xx(u16 vid, u16 pid, int more, int* try_more)
|
||||
static int ft2232_init_ftd2xx(uint16_t vid, uint16_t pid, int more, int* try_more)
|
||||
{
|
||||
FT_STATUS status;
|
||||
DWORD deviceID;
|
||||
|
|
@ -1958,7 +1958,7 @@ static int ft2232_purge_ftd2xx(void)
|
|||
#endif /* BUILD_FT2232_FTD2XX == 1 */
|
||||
|
||||
#if BUILD_FT2232_LIBFTDI == 1
|
||||
static int ft2232_init_libftdi(u16 vid, u16 pid, int more, int* try_more)
|
||||
static int ft2232_init_libftdi(uint16_t vid, uint16_t pid, int more, int* try_more)
|
||||
{
|
||||
uint8_t latency_timer;
|
||||
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@
|
|||
|
||||
|
||||
/* configuration */
|
||||
u16 gw16012_port;
|
||||
uint16_t gw16012_port;
|
||||
|
||||
/* interface variables
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -103,7 +103,7 @@ static cable_t cables[] =
|
|||
|
||||
/* configuration */
|
||||
static char* parport_cable = NULL;
|
||||
static u16 parport_port;
|
||||
static uint16_t parport_port;
|
||||
static int parport_exit = 0;
|
||||
|
||||
/* interface variables
|
||||
|
|
|
|||
|
|
@ -23,8 +23,8 @@
|
|||
typedef
|
||||
struct rlink_speed_table_s {
|
||||
uint8_t const *dtc;
|
||||
u16 dtc_size;
|
||||
u16 khz;
|
||||
uint16_t dtc_size;
|
||||
uint16_t khz;
|
||||
uint8_t prescaler;
|
||||
} rlink_speed_table_t;
|
||||
|
||||
|
|
|
|||
|
|
@ -37,8 +37,8 @@
|
|||
#define VSLLINK_MODE_NORMAL 0
|
||||
#define VSLLINK_MODE_DMA 1
|
||||
|
||||
static u16 vsllink_usb_vid;
|
||||
static u16 vsllink_usb_pid;
|
||||
static uint16_t vsllink_usb_vid;
|
||||
static uint16_t vsllink_usb_pid;
|
||||
static uint8_t vsllink_usb_bulkout;
|
||||
static uint8_t vsllink_usb_bulkin;
|
||||
static uint8_t vsllink_usb_interface;
|
||||
|
|
@ -627,7 +627,7 @@ static int vsllink_connect(void)
|
|||
static void vsllink_append_tms(void)
|
||||
{
|
||||
uint8_t tms_scan = VSLLINK_TAP_MOVE(tap_get_state(), tap_get_end_state());
|
||||
u16 tms2;
|
||||
uint16_t tms2;
|
||||
insert_insignificant_operation_t *insert = \
|
||||
&VSLLINK_TAP_MOVE_INSERT_INSIGNIFICANT[tap_move_ndx(tap_get_state())][tap_move_ndx(tap_get_end_state())];
|
||||
|
||||
|
|
@ -955,7 +955,7 @@ static void vsllink_path_move_dma(int num_states, tap_state_t *path)
|
|||
static void vsllink_stableclocks_normal(int num_cycles, int tms)
|
||||
{
|
||||
int tms_len;
|
||||
u16 tms_append_byte;
|
||||
uint16_t tms_append_byte;
|
||||
|
||||
if (vsllink_tms_data_len > 0)
|
||||
{
|
||||
|
|
@ -965,7 +965,7 @@ static void vsllink_stableclocks_normal(int num_cycles, int tms)
|
|||
if (tms > 0)
|
||||
{
|
||||
// append '1' for tms
|
||||
tms_append_byte = (u16)((((1 << num_cycles) - 1) << vsllink_tms_data_len) & 0xFFFF);
|
||||
tms_append_byte = (uint16_t)((((1 << num_cycles) - 1) << vsllink_tms_data_len) & 0xFFFF);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1092,7 +1092,7 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
|
|||
*/
|
||||
int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
|
||||
{
|
||||
/** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
|
||||
/** \todo TODO: check if buffer cast to u32* and uint16_t* might cause alignment problems */
|
||||
|
||||
FNC_INFO;
|
||||
|
||||
|
|
@ -1148,8 +1148,8 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
|
|||
/* MCR p14,0,R1,c0,c5,0 */
|
||||
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
|
||||
|
||||
u16 svalue = res;
|
||||
memcpy(buffer + count * sizeof(u16), &svalue, sizeof(u16));
|
||||
uint16_t svalue = res;
|
||||
memcpy(buffer + count * sizeof(uint16_t), &svalue, sizeof(uint16_t));
|
||||
}
|
||||
|
||||
break;
|
||||
|
|
@ -1218,8 +1218,8 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
|
|||
|
||||
for (size_t i = 0; i < count; i++)
|
||||
{
|
||||
u16 value;
|
||||
memcpy(&value, buffer + count * sizeof(u16), sizeof(u16));
|
||||
uint16_t value;
|
||||
memcpy(&value, buffer + count * sizeof(uint16_t), sizeof(uint16_t));
|
||||
|
||||
/* MRC p14,0,r1,c0,c5,0 */
|
||||
arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
|
||||
|
|
|
|||
|
|
@ -296,7 +296,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
|
|||
}
|
||||
else
|
||||
{
|
||||
u16 verify = 0xffff;
|
||||
uint16_t verify = 0xffff;
|
||||
/* keep the original instruction in target endianness */
|
||||
if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
|
||||
{
|
||||
|
|
@ -385,7 +385,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
|
|||
}
|
||||
else
|
||||
{
|
||||
u16 current_instr;
|
||||
uint16_t current_instr;
|
||||
/* check that user program as not modified breakpoint instruction */
|
||||
if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)¤t_instr)) != ERROR_OK)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ typedef struct arm7_9_common_s
|
|||
reg_cache_t *eice_cache; /**< Embedded ICE register cache */
|
||||
|
||||
u32 arm_bkpt; /**< ARM breakpoint instruction */
|
||||
u16 thumb_bkpt; /**< Thumb breakpoint instruction */
|
||||
uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */
|
||||
int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
|
||||
int breakpoint_count; /**< Current number of set breakpoints */
|
||||
int wp_available; /**< Current number of available watchpoint units */
|
||||
|
|
|
|||
|
|
@ -396,7 +396,7 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
|
|||
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
||||
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
|
||||
u32 *buf_u32 = buffer;
|
||||
u16 *buf_u16 = buffer;
|
||||
uint16_t *buf_u16 = buffer;
|
||||
uint8_t *buf_u8 = buffer;
|
||||
|
||||
/* STMIA r0-15, [r0] at debug speed
|
||||
|
|
|
|||
|
|
@ -447,7 +447,7 @@ void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
|
|||
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
||||
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
|
||||
u32 *buf_u32 = buffer;
|
||||
u16 *buf_u16 = buffer;
|
||||
uint16_t *buf_u16 = buffer;
|
||||
uint8_t *buf_u8 = buffer;
|
||||
|
||||
/* STMIA r0-15, [r0] at debug speed
|
||||
|
|
|
|||
|
|
@ -599,8 +599,8 @@ int mem_ap_write_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32
|
|||
while (count > 0)
|
||||
{
|
||||
dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
|
||||
u16 svalue;
|
||||
memcpy(&svalue, buffer, sizeof(u16));
|
||||
uint16_t svalue;
|
||||
memcpy(&svalue, buffer, sizeof(uint16_t));
|
||||
u32 outvalue = (u32)svalue << 8 * (address & 0x3);
|
||||
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
|
||||
retval = swjdp_transaction_endcheck(swjdp);
|
||||
|
|
@ -860,8 +860,8 @@ int mem_ap_read_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 a
|
|||
}
|
||||
else
|
||||
{
|
||||
u16 svalue = (invalue >> 8 * (address & 0x3));
|
||||
memcpy(buffer, &svalue, sizeof(u16));
|
||||
uint16_t svalue = (invalue >> 8 * (address & 0x3));
|
||||
memcpy(buffer, &svalue, sizeof(uint16_t));
|
||||
address += 2;
|
||||
buffer += 2;
|
||||
}
|
||||
|
|
@ -1057,7 +1057,7 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i
|
|||
if (romtable_present)
|
||||
{
|
||||
u32 cid0,cid1,cid2,cid3,memtype,romentry;
|
||||
u16 entry_offset;
|
||||
uint16_t entry_offset;
|
||||
/* bit 16 of apid indicates a memory access port */
|
||||
if (dbgbase&0x02)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1319,7 +1319,7 @@ int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
|
|||
return -1;
|
||||
}
|
||||
|
||||
int evaluate_b_bl_blx_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
|
||||
int evaluate_b_bl_blx_thumb(uint16_t opcode, u32 address, arm_instruction_t *instruction)
|
||||
{
|
||||
u32 offset = opcode & 0x7ff;
|
||||
u32 opc = (opcode >> 11) & 0x3;
|
||||
|
|
@ -1366,7 +1366,7 @@ int evaluate_b_bl_blx_thumb(u16 opcode, u32 address, arm_instruction_t *instruct
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int evaluate_add_sub_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
|
||||
int evaluate_add_sub_thumb(uint16_t opcode, u32 address, arm_instruction_t *instruction)
|
||||
{
|
||||
uint8_t Rd = (opcode >> 0) & 0x7;
|
||||
uint8_t Rn = (opcode >> 3) & 0x7;
|
||||
|
|
@ -1408,7 +1408,7 @@ int evaluate_add_sub_thumb(u16 opcode, u32 address, arm_instruction_t *instructi
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int evaluate_shift_imm_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
|
||||
int evaluate_shift_imm_thumb(uint16_t opcode, u32 address, arm_instruction_t *instruction)
|
||||
{
|
||||
uint8_t Rd = (opcode >> 0) & 0x7;
|
||||
uint8_t Rm = (opcode >> 3) & 0x7;
|
||||
|
|
@ -1452,7 +1452,7 @@ int evaluate_shift_imm_thumb(u16 opcode, u32 address, arm_instruction_t *instruc
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int evaluate_data_proc_imm_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
|
||||
int evaluate_data_proc_imm_thumb(uint16_t opcode, u32 address, arm_instruction_t *instruction)
|
||||
{
|
||||
uint8_t imm = opcode & 0xff;
|
||||
uint8_t Rd = (opcode >> 8) & 0x7;
|
||||
|
|
@ -1493,7 +1493,7 @@ int evaluate_data_proc_imm_thumb(u16 opcode, u32 address, arm_instruction_t *ins
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int evaluate_data_proc_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
|
||||
int evaluate_data_proc_thumb(uint16_t opcode, u32 address, arm_instruction_t *instruction)
|
||||
{
|
||||
uint8_t high_reg, op, Rm, Rd,H1,H2;
|
||||
char *mnemonic = NULL;
|
||||
|
|
@ -1652,7 +1652,7 @@ int evaluate_data_proc_thumb(u16 opcode, u32 address, arm_instruction_t *instruc
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int evaluate_load_literal_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
|
||||
int evaluate_load_literal_thumb(uint16_t opcode, u32 address, arm_instruction_t *instruction)
|
||||
{
|
||||
u32 immediate;
|
||||
uint8_t Rd = (opcode >> 8) & 0x7;
|
||||
|
|
@ -1671,7 +1671,7 @@ int evaluate_load_literal_thumb(u16 opcode, u32 address, arm_instruction_t *inst
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int evaluate_load_store_reg_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
|
||||
int evaluate_load_store_reg_thumb(uint16_t opcode, u32 address, arm_instruction_t *instruction)
|
||||
{
|
||||
uint8_t Rd = (opcode >> 0) & 0x7;
|
||||
uint8_t Rn = (opcode >> 3) & 0x7;
|
||||
|
|
@ -1726,7 +1726,7 @@ int evaluate_load_store_reg_thumb(u16 opcode, u32 address, arm_instruction_t *in
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int evaluate_load_store_imm_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
|
||||
int evaluate_load_store_imm_thumb(uint16_t opcode, u32 address, arm_instruction_t *instruction)
|
||||
{
|
||||
u32 offset = (opcode >> 6) & 0x1f;
|
||||
uint8_t Rd = (opcode >> 0) & 0x7;
|
||||
|
|
@ -1770,7 +1770,7 @@ int evaluate_load_store_imm_thumb(u16 opcode, u32 address, arm_instruction_t *in
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int evaluate_load_store_stack_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
|
||||
int evaluate_load_store_stack_thumb(uint16_t opcode, u32 address, arm_instruction_t *instruction)
|
||||
{
|
||||
u32 offset = opcode & 0xff;
|
||||
uint8_t Rd = (opcode >> 8) & 0x7;
|
||||
|
|
@ -1799,7 +1799,7 @@ int evaluate_load_store_stack_thumb(u16 opcode, u32 address, arm_instruction_t *
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int evaluate_add_sp_pc_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
|
||||
int evaluate_add_sp_pc_thumb(uint16_t opcode, u32 address, arm_instruction_t *instruction)
|
||||
{
|
||||
u32 imm = opcode & 0xff;
|
||||
uint8_t Rd = (opcode >> 8) & 0x7;
|
||||
|
|
@ -1830,7 +1830,7 @@ int evaluate_add_sp_pc_thumb(u16 opcode, u32 address, arm_instruction_t *instruc
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int evaluate_adjust_stack_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
|
||||
int evaluate_adjust_stack_thumb(uint16_t opcode, u32 address, arm_instruction_t *instruction)
|
||||
{
|
||||
u32 imm = opcode & 0x7f;
|
||||
uint8_t opc = opcode & (1<<7);
|
||||
|
|
@ -1858,7 +1858,7 @@ int evaluate_adjust_stack_thumb(u16 opcode, u32 address, arm_instruction_t *inst
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int evaluate_breakpoint_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
|
||||
int evaluate_breakpoint_thumb(uint16_t opcode, u32 address, arm_instruction_t *instruction)
|
||||
{
|
||||
u32 imm = opcode & 0xff;
|
||||
|
||||
|
|
@ -1869,7 +1869,7 @@ int evaluate_breakpoint_thumb(u16 opcode, u32 address, arm_instruction_t *instru
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int evaluate_load_store_multiple_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
|
||||
int evaluate_load_store_multiple_thumb(uint16_t opcode, u32 address, arm_instruction_t *instruction)
|
||||
{
|
||||
u32 reg_list = opcode & 0xff;
|
||||
u32 L = opcode & (1<<11);
|
||||
|
|
@ -1936,7 +1936,7 @@ int evaluate_load_store_multiple_thumb(u16 opcode, u32 address, arm_instruction_
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int evaluate_cond_branch_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
|
||||
int evaluate_cond_branch_thumb(uint16_t opcode, u32 address, arm_instruction_t *instruction)
|
||||
{
|
||||
u32 offset = opcode & 0xff;
|
||||
uint8_t cond = (opcode >> 8) & 0xf;
|
||||
|
|
@ -1971,7 +1971,7 @@ int evaluate_cond_branch_thumb(u16 opcode, u32 address, arm_instruction_t *instr
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int thumb_evaluate_opcode(u16 opcode, u32 address, arm_instruction_t *instruction)
|
||||
int thumb_evaluate_opcode(uint16_t opcode, u32 address, arm_instruction_t *instruction)
|
||||
{
|
||||
/* clear fields, to avoid confusion */
|
||||
memset(instruction, 0, sizeof(arm_instruction_t));
|
||||
|
|
|
|||
|
|
@ -195,7 +195,7 @@ typedef struct arm_instruction_s
|
|||
} arm_instruction_t;
|
||||
|
||||
extern int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction);
|
||||
extern int thumb_evaluate_opcode(u16 opcode, u32 address, arm_instruction_t *instruction);
|
||||
extern int thumb_evaluate_opcode(uint16_t opcode, u32 address, arm_instruction_t *instruction);
|
||||
extern int arm_access_size(arm_instruction_t *instruction);
|
||||
|
||||
#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28])
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@ int arm_jtag_buf_to_le32_flip(uint8_t *in_buf, void *priv, struct scan_field_s *
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* read JTAG buffer into little-endian u16, flipping bit-order */
|
||||
/* read JTAG buffer into little-endian uint16_t, flipping bit-order */
|
||||
int arm_jtag_buf_to_le16_flip(uint8_t *in_buf, void *priv, struct scan_field_s *field)
|
||||
{
|
||||
h_u16_to_le(((uint8_t*)priv), flip_u32(le_to_h_u32(in_buf), 32) & 0xffff);
|
||||
|
|
@ -144,7 +144,7 @@ int arm_jtag_buf_to_be32_flip(uint8_t *in_buf, void *priv, struct scan_field_s *
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* read JTAG buffer into big-endian u16, flipping bit-order */
|
||||
/* read JTAG buffer into big-endian uint16_t, flipping bit-order */
|
||||
int arm_jtag_buf_to_be16_flip(uint8_t *in_buf, void *priv, struct scan_field_s *field)
|
||||
{
|
||||
h_u16_to_be(((uint8_t*)priv), flip_u32(le_to_h_u32(in_buf), 32) & 0xffff);
|
||||
|
|
@ -175,7 +175,7 @@ int arm_jtag_buf_to_le32(uint8_t *in_buf, void *priv, struct scan_field_s *field
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* read JTAG buffer into little-endian u16 */
|
||||
/* read JTAG buffer into little-endian uint16_t */
|
||||
int arm_jtag_buf_to_le16(uint8_t *in_buf, void *priv, struct scan_field_s *field)
|
||||
{
|
||||
h_u16_to_le(((uint8_t*)priv), le_to_h_u32(in_buf) & 0xffff);
|
||||
|
|
@ -189,7 +189,7 @@ int arm_jtag_buf_to_be32(uint8_t *in_buf, void *priv, struct scan_field_s *field
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* read JTAG buffer into big-endian u16 */
|
||||
/* read JTAG buffer into big-endian uint16_t */
|
||||
int arm_jtag_buf_to_be16(uint8_t *in_buf, void *priv, struct scan_field_s *field)
|
||||
{
|
||||
h_u16_to_be(((uint8_t*)priv), le_to_h_u32(in_buf) & 0xffff);
|
||||
|
|
|
|||
|
|
@ -258,7 +258,7 @@ int pass_condition(u32 cpsr, u32 opcode)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int thumb_pass_branch_condition(u32 cpsr, u16 opcode)
|
||||
int thumb_pass_branch_condition(u32 cpsr, uint16_t opcode)
|
||||
{
|
||||
return pass_condition(cpsr, (opcode & 0x0f00) << 20);
|
||||
}
|
||||
|
|
@ -307,7 +307,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
|
|||
}
|
||||
else
|
||||
{
|
||||
u16 opcode;
|
||||
uint16_t opcode;
|
||||
|
||||
if((retval = target_read_u16(target, current_pc, &opcode)) != ERROR_OK)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -393,7 +393,7 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
|
|||
int i;
|
||||
arm_instruction_t cur_instruction;
|
||||
u32 opcode;
|
||||
u16 thumb_opcode;
|
||||
uint16_t thumb_opcode;
|
||||
int thumb = 0;
|
||||
|
||||
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
|
||||
|
|
|
|||
|
|
@ -560,7 +560,7 @@ int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32*
|
|||
reg_param_t reg_params[2];
|
||||
int retval;
|
||||
|
||||
u16 cortex_m3_crc_code[] = {
|
||||
uint16_t cortex_m3_crc_code[] = {
|
||||
0x4602, /* mov r2, r0 */
|
||||
0xF04F, 0x30FF, /* mov r0, #0xffffffff */
|
||||
0x460B, /* mov r3, r1 */
|
||||
|
|
@ -599,8 +599,8 @@ int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32*
|
|||
}
|
||||
|
||||
/* convert flash writing code into a buffer in target endianness */
|
||||
for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(u16)); i++)
|
||||
if((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(u16), cortex_m3_crc_code[i])) != ERROR_OK)
|
||||
for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(uint16_t)); i++)
|
||||
if((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK)
|
||||
{
|
||||
return retval;
|
||||
}
|
||||
|
|
@ -642,7 +642,7 @@ int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u
|
|||
int retval;
|
||||
u32 i;
|
||||
|
||||
u16 erase_check_code[] =
|
||||
uint16_t erase_check_code[] =
|
||||
{
|
||||
/* loop: */
|
||||
0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
|
||||
|
|
@ -660,8 +660,8 @@ int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u
|
|||
}
|
||||
|
||||
/* convert flash writing code into a buffer in target endianness */
|
||||
for (i = 0; i < (sizeof(erase_check_code)/sizeof(u16)); i++)
|
||||
target_write_u16(target, erase_check_algorithm->address + i*sizeof(u16), erase_check_code[i]);
|
||||
for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint16_t)); i++)
|
||||
target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
|
||||
|
||||
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
|
||||
armv7m_info.core_mode = ARMV7M_MODE_ANY;
|
||||
|
|
|
|||
|
|
@ -54,8 +54,8 @@ int mcu_write_ir(jtag_tap_t *tap, uint8_t *ir_in, uint8_t *ir_out, int ir_len, i
|
|||
int mcu_write_dr(jtag_tap_t *tap, uint8_t *dr_in, uint8_t *dr_out, int dr_len, int rti);
|
||||
int mcu_write_ir_u8(jtag_tap_t *tap, uint8_t *ir_in, uint8_t ir_out, int ir_len, int rti);
|
||||
int mcu_write_dr_u8(jtag_tap_t *tap, uint8_t *ir_in, uint8_t ir_out, int dr_len, int rti);
|
||||
int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti);
|
||||
int mcu_write_dr_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int dr_len, int rti);
|
||||
int mcu_write_ir_u16(jtag_tap_t *tap, uint16_t *ir_in, uint16_t ir_out, int ir_len, int rti);
|
||||
int mcu_write_dr_u16(jtag_tap_t *tap, uint16_t *ir_in, uint16_t ir_out, int dr_len, int rti);
|
||||
int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti);
|
||||
int mcu_write_dr_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int dr_len, int rti);
|
||||
int mcu_execute_queue(void);
|
||||
|
|
@ -271,7 +271,7 @@ int mcu_write_dr_u8(jtag_tap_t *tap, uint8_t *dr_in, uint8_t dr_out, int dr_len,
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti)
|
||||
int mcu_write_ir_u16(jtag_tap_t *tap, uint16_t *ir_in, uint16_t ir_out, int ir_len, int rti)
|
||||
{
|
||||
if (ir_len > 16)
|
||||
{
|
||||
|
|
@ -284,7 +284,7 @@ int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rt
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mcu_write_dr_u16(jtag_tap_t *tap, u16 *dr_in, u16 dr_out, int dr_len, int rti)
|
||||
int mcu_write_dr_u16(jtag_tap_t *tap, uint16_t *dr_in, uint16_t dr_out, int dr_len, int rti)
|
||||
{
|
||||
if (dr_len > 16)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@ target_type_t cortexa8_target =
|
|||
|
||||
int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
|
||||
{
|
||||
u16 dcrdr;
|
||||
uint16_t dcrdr;
|
||||
|
||||
mem_ap_read_buf_u16( swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
|
||||
*ctrl = (uint8_t)dcrdr;
|
||||
|
|
|
|||
|
|
@ -1489,7 +1489,7 @@ int cortex_m3_quit(void)
|
|||
|
||||
int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
|
||||
{
|
||||
u16 dcrdr;
|
||||
uint16_t dcrdr;
|
||||
|
||||
mem_ap_read_buf_u16( swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
|
||||
*ctrl = (uint8_t)dcrdr;
|
||||
|
|
|
|||
|
|
@ -128,7 +128,7 @@ enum
|
|||
typedef struct etmv1_trace_data_s
|
||||
{
|
||||
uint8_t pipestat; /* bits 0-2 pipeline status */
|
||||
u16 packet; /* packet data (4, 8 or 16 bit) */
|
||||
uint16_t packet; /* packet data (4, 8 or 16 bit) */
|
||||
int flags; /* ETMV1_TRACESYNC_CYCLE, ETMV1_TRIGGER_CYCLE */
|
||||
} etmv1_trace_data_t;
|
||||
|
||||
|
|
|
|||
|
|
@ -239,7 +239,7 @@ void feroceon_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
|
|||
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
||||
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
|
||||
u32 *buf_u32 = buffer;
|
||||
u16 *buf_u16 = buffer;
|
||||
uint16_t *buf_u16 = buffer;
|
||||
uint8_t *buf_u8 = buffer;
|
||||
|
||||
arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
|
||||
|
|
|
|||
|
|
@ -236,7 +236,7 @@ static int image_ihex_buffer_complete(image_t *image)
|
|||
}
|
||||
else if (record_type == 2) /* Linear Address Record */
|
||||
{
|
||||
u16 upper_address;
|
||||
uint16_t upper_address;
|
||||
|
||||
sscanf(&lpszLine[bytes_read], "%4hx", &upper_address);
|
||||
cal_checksum += (uint8_t)(upper_address >> 8);
|
||||
|
|
@ -276,7 +276,7 @@ static int image_ihex_buffer_complete(image_t *image)
|
|||
}
|
||||
else if (record_type == 4) /* Extended Linear Address Record */
|
||||
{
|
||||
u16 upper_address;
|
||||
uint16_t upper_address;
|
||||
|
||||
sscanf(&lpszLine[bytes_read], "%4hx", &upper_address);
|
||||
cal_checksum += (uint8_t)(upper_address >> 8);
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@ begin_ejtag_dma_read:
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data)
|
||||
static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, uint16_t *data)
|
||||
{
|
||||
u32 v;
|
||||
u32 ejtag_ctrl;
|
||||
|
|
@ -356,7 +356,7 @@ int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int cou
|
|||
case 1:
|
||||
return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t*)buf);
|
||||
case 2:
|
||||
return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (u16*)buf);
|
||||
return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t*)buf);
|
||||
case 4:
|
||||
return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (u32*)buf);
|
||||
}
|
||||
|
|
@ -377,7 +377,7 @@ int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
|
||||
int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uint16_t *buf)
|
||||
{
|
||||
int i;
|
||||
int retval;
|
||||
|
|
@ -410,7 +410,7 @@ int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int co
|
|||
case 1:
|
||||
return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (uint8_t*)buf);
|
||||
case 2:
|
||||
return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(u16*)buf);
|
||||
return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(uint16_t*)buf);
|
||||
case 4:
|
||||
return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (u32*)buf);
|
||||
}
|
||||
|
|
@ -431,7 +431,7 @@ int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
|
||||
int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uint16_t *buf)
|
||||
{
|
||||
int i;
|
||||
int retval;
|
||||
|
|
|
|||
|
|
@ -38,11 +38,11 @@ extern int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size,
|
|||
extern int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
|
||||
|
||||
extern int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, uint8_t *buf);
|
||||
extern int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf);
|
||||
extern int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uint16_t *buf);
|
||||
extern int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf);
|
||||
|
||||
extern int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, uint8_t *buf);
|
||||
extern int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf);
|
||||
extern int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uint16_t *buf);
|
||||
extern int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -276,7 +276,7 @@ int mips32_pracc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int coun
|
|||
case 1:
|
||||
return mips32_pracc_read_mem8(ejtag_info, addr, count, (uint8_t*)buf);
|
||||
case 2:
|
||||
return mips32_pracc_read_mem16(ejtag_info, addr, count, (u16*)buf);
|
||||
return mips32_pracc_read_mem16(ejtag_info, addr, count, (uint16_t*)buf);
|
||||
case 4:
|
||||
if(count==1)
|
||||
return mips32_pracc_read_u32(ejtag_info, addr, (u32*)buf);
|
||||
|
|
@ -395,7 +395,7 @@ int mips32_pracc_read_u32(mips_ejtag_t *ejtag_info, u32 addr, u32 *buf)
|
|||
return retval;
|
||||
}
|
||||
|
||||
int mips32_pracc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
|
||||
int mips32_pracc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uint16_t *buf)
|
||||
{
|
||||
u32 code[] = {
|
||||
/* start: */
|
||||
|
|
@ -560,7 +560,7 @@ int mips32_pracc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int cou
|
|||
case 1:
|
||||
return mips32_pracc_write_mem8(ejtag_info, addr, count, (uint8_t*)buf);
|
||||
case 2:
|
||||
return mips32_pracc_write_mem16(ejtag_info, addr, count,(u16*)buf);
|
||||
return mips32_pracc_write_mem16(ejtag_info, addr, count,(uint16_t*)buf);
|
||||
case 4:
|
||||
if(count==1)
|
||||
return mips32_pracc_write_u32(ejtag_info, addr, (u32*)buf);
|
||||
|
|
@ -653,7 +653,7 @@ int mips32_pracc_write_u32(mips_ejtag_t *ejtag_info, u32 addr, u32 *buf)
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips32_pracc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
|
||||
int mips32_pracc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uint16_t *buf)
|
||||
{
|
||||
u32 code[] = {
|
||||
/* start: */
|
||||
|
|
|
|||
|
|
@ -41,12 +41,12 @@ extern int mips32_pracc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, i
|
|||
extern int mips32_pracc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
|
||||
|
||||
extern int mips32_pracc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, uint8_t *buf);
|
||||
extern int mips32_pracc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf);
|
||||
extern int mips32_pracc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uint16_t *buf);
|
||||
extern int mips32_pracc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf);
|
||||
extern int mips32_pracc_read_u32(mips_ejtag_t *ejtag_info, u32 addr, u32 *buf);
|
||||
|
||||
extern int mips32_pracc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, uint8_t *buf);
|
||||
extern int mips32_pracc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf);
|
||||
extern int mips32_pracc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uint16_t *buf);
|
||||
extern int mips32_pracc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf);
|
||||
extern int mips32_pracc_write_u32(mips_ejtag_t *ejtag_info, u32 addr, u32 *buf);
|
||||
|
||||
|
|
|
|||
|
|
@ -552,7 +552,7 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
|
|||
}
|
||||
else
|
||||
{
|
||||
u16 verify = 0xffff;
|
||||
uint16_t verify = 0xffff;
|
||||
|
||||
if((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
|
||||
{
|
||||
|
|
@ -627,7 +627,7 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
|
|||
}
|
||||
else
|
||||
{
|
||||
u16 current_instr;
|
||||
uint16_t current_instr;
|
||||
|
||||
/* check that user program has not modified breakpoint instruction */
|
||||
if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)¤t_instr)) != ERROR_OK)
|
||||
|
|
@ -761,7 +761,7 @@ int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 cou
|
|||
if (target->endianness == TARGET_BIG_ENDIAN)
|
||||
{
|
||||
u32 i, t32;
|
||||
u16 t16;
|
||||
uint16_t t16;
|
||||
|
||||
for(i = 0; i < (count*size); i += size)
|
||||
{
|
||||
|
|
@ -806,7 +806,7 @@ int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 co
|
|||
if (target->endianness == TARGET_BIG_ENDIAN)
|
||||
{
|
||||
u32 i, t32;
|
||||
u16 t16;
|
||||
uint16_t t16;
|
||||
|
||||
for(i = 0; i < (count*size); i += size)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -280,8 +280,8 @@ u32 target_buffer_get_u32(target_t *target, const uint8_t *buffer)
|
|||
return be_to_h_u32(buffer);
|
||||
}
|
||||
|
||||
/* read a u16 from a buffer in target memory endianness */
|
||||
u16 target_buffer_get_u16(target_t *target, const uint8_t *buffer)
|
||||
/* read a uint16_t from a buffer in target memory endianness */
|
||||
uint16_t target_buffer_get_u16(target_t *target, const uint8_t *buffer)
|
||||
{
|
||||
if (target->endianness == TARGET_LITTLE_ENDIAN)
|
||||
return le_to_h_u16(buffer);
|
||||
|
|
@ -304,8 +304,8 @@ void target_buffer_set_u32(target_t *target, uint8_t *buffer, u32 value)
|
|||
h_u32_to_be(buffer, value);
|
||||
}
|
||||
|
||||
/* write a u16 to a buffer in target memory endianness */
|
||||
void target_buffer_set_u16(target_t *target, uint8_t *buffer, u16 value)
|
||||
/* write a uint16_t to a buffer in target memory endianness */
|
||||
void target_buffer_set_u16(target_t *target, uint8_t *buffer, uint16_t value)
|
||||
{
|
||||
if (target->endianness == TARGET_LITTLE_ENDIAN)
|
||||
h_u16_to_le(buffer, value);
|
||||
|
|
@ -1328,7 +1328,7 @@ int target_read_u32(struct target_s *target, u32 address, u32 *value)
|
|||
return retval;
|
||||
}
|
||||
|
||||
int target_read_u16(struct target_s *target, u32 address, u16 *value)
|
||||
int target_read_u16(struct target_s *target, u32 address, uint16_t *value)
|
||||
{
|
||||
uint8_t value_buf[2];
|
||||
if (!target_was_examined(target))
|
||||
|
|
@ -1396,7 +1396,7 @@ int target_write_u32(struct target_s *target, u32 address, u32 value)
|
|||
return retval;
|
||||
}
|
||||
|
||||
int target_write_u16(struct target_s *target, u32 address, u16 value)
|
||||
int target_write_u16(struct target_s *target, u32 address, uint16_t value)
|
||||
{
|
||||
int retval;
|
||||
uint8_t value_buf[2];
|
||||
|
|
|
|||
|
|
@ -380,17 +380,17 @@ extern target_event_callback_t *target_event_callbacks;
|
|||
extern target_timer_callback_t *target_timer_callbacks;
|
||||
|
||||
extern u32 target_buffer_get_u32(target_t *target, const uint8_t *buffer);
|
||||
extern u16 target_buffer_get_u16(target_t *target, const uint8_t *buffer);
|
||||
extern uint16_t target_buffer_get_u16(target_t *target, const uint8_t *buffer);
|
||||
extern uint8_t target_buffer_get_u8 (target_t *target, const uint8_t *buffer);
|
||||
extern void target_buffer_set_u32(target_t *target, uint8_t *buffer, u32 value);
|
||||
extern void target_buffer_set_u16(target_t *target, uint8_t *buffer, u16 value);
|
||||
extern void target_buffer_set_u16(target_t *target, uint8_t *buffer, uint16_t value);
|
||||
extern void target_buffer_set_u8 (target_t *target, uint8_t *buffer, uint8_t value);
|
||||
|
||||
int target_read_u32(struct target_s *target, u32 address, u32 *value);
|
||||
int target_read_u16(struct target_s *target, u32 address, u16 *value);
|
||||
int target_read_u16(struct target_s *target, u32 address, uint16_t *value);
|
||||
int target_read_u8(struct target_s *target, u32 address, uint8_t *value);
|
||||
int target_write_u32(struct target_s *target, u32 address, u32 value);
|
||||
int target_write_u16(struct target_s *target, u32 address, u16 value);
|
||||
int target_write_u16(struct target_s *target, u32 address, uint16_t value);
|
||||
int target_write_u8(struct target_s *target, u32 address, uint8_t value);
|
||||
|
||||
/* Issues USER() statements with target state information */
|
||||
|
|
|
|||
|
|
@ -125,7 +125,7 @@ typedef struct xscale_common_s
|
|||
int ibcr0_used;
|
||||
int ibcr1_used;
|
||||
u32 arm_bkpt;
|
||||
u16 thumb_bkpt;
|
||||
uint16_t thumb_bkpt;
|
||||
|
||||
uint8_t vector_catch;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue