interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

- fix issue with jlink/libusb timeout under linux 

- add missing svn props

git-svn-id: svn://svn.berlios.de/openocd/trunk@1128 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
ntfreak 2008-11-03 14:27:57 +00:00
parent 8a7464df2d
commit f809ee6935
2 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/jtag/jlink.c
View File

@ -52,7 +52,7 @@
#define JLINK_WRITE_ENDPOINT 0x02
#define JLINK_READ_ENDPOINT 0x81
#define JLINK_USB_TIMEOUT 100
#define JLINK_USB_TIMEOUT 1000
#define JLINK_IN_BUFFER_SIZE 8192
#define JLINK_OUT_BUFFER_SIZE 8192

24
src/target/target/imx27.cfg
View File

@ -1,12 +1,12 @@
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
# There are 2 taps on the chip:
# The ETM
jtag_device 4 0x1 0xf 0xe
# The ARM926EJS
jtag_device 4 0x1 0xf 0xe
# Note above there are 2 taps (#0 and #1) the ARM926 is the 2nd tap (ie #1)
target create target0 arm926ejs -endianess little -chain-position 1 -variant arm926ejs
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
# There are 2 taps on the chip:
# The ETM
jtag_device 4 0x1 0xf 0xe
# The ARM926EJS
jtag_device 4 0x1 0xf 0xe
# Note above there are 2 taps (#0 and #1) the ARM926 is the 2nd tap (ie #1)
target create target0 arm926ejs -endianess little -chain-position 1 -variant arm926ejs