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riscv-openocd
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Successfully determine xlen. 

There's a nop in there for no reason, though.
This commit is contained in:
Tim Newsome 2016-06-03 17:47:17 -07:00
parent db06dd45a0
commit f634702aaf
2 changed files with 49 additions and 9 deletions
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14
src/target/riscv/opcodes.h
View File

@ -114,6 +114,18 @@ static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm)
} }
/* /*
static uint32_t li(unsigned int dest, uint16_t imm)
{
return addi(dest, 0, imm);
}
static uint32_t lui(unsigned int dest, uint32_t imm)
{
return (bits(imm, 19, 0) << 12) |
(dest << 7) |
MATCH_LUI;
}
static uint32_t csrr(unsigned int rd, unsigned int csr) { static uint32_t csrr(unsigned int rd, unsigned int csr) {
return (csr << 20) | (rd << 7) | MATCH_CSRRS; return (csr << 20) | (rd << 7) | MATCH_CSRRS;
} }
@ -165,9 +177,9 @@ static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm)
(dest << 7) | (dest << 7) |
MATCH_ORI; MATCH_ORI;
} }
*/
static uint32_t nop(void) static uint32_t nop(void)
{ {
return addi(0, 0, 0); return addi(0, 0, 0);
} }
*/

44
src/target/riscv/riscv.c
View File

@ -255,8 +255,7 @@ static uint32_t dtminfo_read(struct target *target)
return buf_get_u32(field.in_value, 0, 32); return buf_get_u32(field.in_value, 0, 32);
} }
static uint32_t dram_read32(struct target *target, unsigned int index, static uint32_t dram_read32(struct target *target, unsigned int index)
bool set_interrupt)
{ {
// TODO: check cache to see if this even needs doing. // TODO: check cache to see if this even needs doing.
uint16_t address = dram_address(index); uint16_t address = dram_address(index);
@ -276,7 +275,7 @@ static void dram_write32(struct target *target, unsigned int index, uint32_t val
static int dram_check32(struct target *target, unsigned int index, static int dram_check32(struct target *target, unsigned int index,
uint32_t expected) uint32_t expected)
{ {
uint32_t actual = dram_read32(target, index, false); uint32_t actual = dram_read32(target, index);
if (expected != actual) { if (expected != actual) {
LOG_ERROR("Wrote 0x%x to Debug RAM at %d, but read back 0x%x", LOG_ERROR("Wrote 0x%x to Debug RAM at %d, but read back 0x%x",
expected, index, actual); expected, index, actual);
@ -493,7 +492,7 @@ static int riscv_examine(struct target *target)
if (get_field(dminfo, DMINFO_VERSION) != 1) { if (get_field(dminfo, DMINFO_VERSION) != 1) {
LOG_ERROR("OpenOCD only supports Debug Module version 1, not %d", LOG_ERROR("OpenOCD only supports Debug Module version 1, not %d",
get_field(dminfo, DMINFO_VERSION)); get_field(dminfo, DMINFO_VERSION));
return ERROR_FAIL; //TODO return ERROR_FAIL;
} }
info->dramsize = get_field(dminfo, DMINFO_DRAMSIZE) + 1; info->dramsize = get_field(dminfo, DMINFO_DRAMSIZE) + 1;
@ -505,7 +504,7 @@ static int riscv_examine(struct target *target)
if (get_field(dminfo, DMINFO_AUTHTYPE) != 0) { if (get_field(dminfo, DMINFO_AUTHTYPE) != 0) {
LOG_ERROR("Authentication required by RISC-V core but not " LOG_ERROR("Authentication required by RISC-V core but not "
"supported by OpenOCD. dminfo=0x%x", dminfo); "supported by OpenOCD. dminfo=0x%x", dminfo);
return ERROR_FAIL; //TODO return ERROR_FAIL;
} }
// Figure out XLEN. // Figure out XLEN.
@ -529,16 +528,45 @@ static int riscv_examine(struct target *target)
return ERROR_FAIL; return ERROR_FAIL;
} }
dram_write32(target, 5, nop(), false);
// Execute. // Execute.
dram_write_jump(target, 5, true); dram_write_jump(target, 6, true);
//dram_read32(target, 5);
//dbus_scan(target, NULL, DBUS_OP_NOP, 0, DMCONTROL_INTERRUPT | DMCONTROL_HALTNOT);
#if 0
// light up LED and hang
dram_write32(target, 0, lui(S0, 0x70002), false);
dram_write32(target, 1, li(S1, 0xa0), false);
dram_write32(target, 2, sw(S1, S0, 0xa0), false);
dram_write32(target, 3, jal(0, 0), true);
#endif
#if 0
// Jump right back.
dram_write_jump(target, 0, false);
dram_write_jump(target, 0, true);
if (wait_for_debugint_clear(target) != ERROR_OK) {
LOG_ERROR("Debug interrupt didn't clear.");
// TODO: return ERROR_FAIL;
}
#endif
#if 0
// Clear the first word in debug RAM
dram_write32(target, 0, sw(ZERO, ZERO, DEBUG_RAM_START), false);
dram_write32(target, 1, 0x0ff0000f, false);
dram_write_jump(target, 2, true);
#endif
if (wait_for_debugint_clear(target) != ERROR_OK) { if (wait_for_debugint_clear(target) != ERROR_OK) {
LOG_ERROR("Debug interrupt didn't clear."); LOG_ERROR("Debug interrupt didn't clear.");
// TODO: return ERROR_FAIL; // TODO: return ERROR_FAIL;
} }
uint32_t word0 = dram_read32(target, 0, false); uint32_t word0 = dram_read32(target, 0);
uint32_t word1 = dram_read32(target, 1, false); uint32_t word1 = dram_read32(target, 1);
if (word0 == 1 && word1 == 0) { if (word0 == 1 && word1 == 0) {
info->xlen = 32; info->xlen = 32;
} else if (word0 == 0xffffffff && word1 == 3) { } else if (word0 == 0xffffffff && word1 == 3) {