interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

cortex_a: remove ahb support for phys_memory access 

Change-Id: I5b7c21c16e95cc1a3160e356d6e64f1f8c449e6e
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2795
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Oleksij Rempel 2015-05-15 09:02:22 +02:00 committed by Paul Fertser
parent bfba15a898
commit f478107d02
1 changed files with 14 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
src/target/cortex_a.c
View File

@ -2611,29 +2611,20 @@ static int cortex_a_read_phys_memory(struct target *target,
uint32_t count, uint8_t *buffer) uint32_t count, uint8_t *buffer)
{ {
struct armv7a_common *armv7a = target_to_armv7a(target); struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval = ERROR_COMMAND_SYNTAX_ERROR; int retval = ERROR_COMMAND_SYNTAX_ERROR;
uint8_t apsel = swjdp->apsel;
LOG_DEBUG("Reading memory at real address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, LOG_DEBUG("Reading memory at real address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32,
address, size, count); address, size, count);
if (count && buffer) { if (count && buffer) {
/* read memory through APB-AP */
if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) { if (!armv7a->is_armv7r) {
/* disable mmu */
/* read memory through AHB-AP */ retval = cortex_a_mmu_modify(target, 0);
retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap, buffer, size, count, address); if (retval != ERROR_OK)
} else { return retval;
/* read memory through APB-AP */
if (!armv7a->is_armv7r) {
/* disable mmu */
retval = cortex_a_mmu_modify(target, 0);
if (retval != ERROR_OK)
return retval;
}
retval = cortex_a_read_apb_ab_memory(target, address, size, count, buffer);
} }
retval = cortex_a_read_apb_ab_memory(target, address, size, count, buffer);
} }
return retval; return retval;
} }
@ -2692,32 +2683,21 @@ static int cortex_a_write_phys_memory(struct target *target,
uint32_t count, const uint8_t *buffer) uint32_t count, const uint8_t *buffer)
{ {
struct armv7a_common *armv7a = target_to_armv7a(target); struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval = ERROR_COMMAND_SYNTAX_ERROR; int retval = ERROR_COMMAND_SYNTAX_ERROR;
uint8_t apsel = swjdp->apsel;
LOG_DEBUG("Writing memory to real address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address, LOG_DEBUG("Writing memory to real address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
size, count); size, count);
if (count && buffer) { if (count && buffer) {
/* write memory through APB-AP */
if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) { if (!armv7a->is_armv7r) {
retval = cortex_a_mmu_modify(target, 0);
/* write memory through AHB-AP */ if (retval != ERROR_OK)
retval = mem_ap_sel_write_buf(swjdp, armv7a->memory_ap, buffer, size, count, address); return retval;
} else {
/* write memory through APB-AP */
if (!armv7a->is_armv7r) {
retval = cortex_a_mmu_modify(target, 0);
if (retval != ERROR_OK)
return retval;
}
return cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
} }
return cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
} }
/* REVISIT this op is generic ARMv7-A/R stuff */ /* REVISIT this op is generic ARMv7-A/R stuff */
if (retval == ERROR_OK && target->state == TARGET_HALTED) { if (retval == ERROR_OK && target->state == TARGET_HALTED) {
struct arm_dpm *dpm = armv7a->arm.dpm; struct arm_dpm *dpm = armv7a->arm.dpm;