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arm920t: memory writes were broken when MMU was disabled 

To support breakpoints, flush data cache line and invalidate
instruction cache when 4 and 2 byte words are written.

The previous code was trying to write directly to the physical
memory, which was buggy and had a number of other situations
that were not handled.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This commit is contained in:
Øyvind Harboe 2009-11-03 12:28:00 +01:00
parent b5ce7fe812
commit f37c9b8d15
1 changed files with 10 additions and 11 deletions
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21
src/target/arm920t.c
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@ -555,26 +555,25 @@ int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t siz
if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK) if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
return retval; return retval;
/* This fn is used to write breakpoints, so we need to make sure that the
* datacache is flushed and the instruction cache is invalidated */
if (((size == 4) || (size == 2)) && (count == 1)) if (((size == 4) || (size == 2)) && (count == 1))
{ {
if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
{ {
LOG_DEBUG("D-Cache enabled, writing through to main memory"); LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
uint32_t pa, cb, ap; /* MCR p15,0,Rd,c7,c10,2 */
int type, domain; retval = arm920t_write_cp15_interpreted(target, 0xee070f5e, 0x0, address);
if (retval != ERROR_OK)
pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap); return retval;
if (type == -1)
return ERROR_OK;
/* cacheable & bufferable means write-back region */
if (cb == 3)
armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
} }
if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled) if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
{ {
LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line"); LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address); retval = arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
if (retval != ERROR_OK)
return retval;
} }
} }