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Matt Hsu <matt@0xlab.org> Wait for the DTRRX to be full before reading it. Remove the trans_mode change as it is done in the mem_ap_read_atomic_u32 function. 

git-svn-id: svn://svn.berlios.de/openocd/trunk@2633 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe 2009-08-26 19:20:25 +00:00
parent 56b346447b
commit f36d0083de
1 changed files with 9 additions and 4 deletions
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13
src/target/cortex_a8.c
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@ -259,14 +259,13 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
{ {
int retval = ERROR_OK; int retval = ERROR_OK;
uint8_t reg = regnum&0xFF; uint8_t reg = regnum&0xFF;
uint32_t dscr;
/* get pointers to arch-specific information */ /* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info; armv7a_common_t *armv7a = armv4_5->arch_info;
swjdp_common_t *swjdp = &armv7a->swjdp_info; swjdp_common_t *swjdp = &armv7a->swjdp_info;
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
if (reg > 16) if (reg > 16)
return retval; return retval;
@ -286,10 +285,16 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0)); cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
} }
/* Read DCCTX */ /* Read DTRRTX */
do
{
retval = mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
}
while ((dscr & (1 << 29)) == 0); /* Wait for DTRRXfull */
retval = mem_ap_read_atomic_u32(swjdp, retval = mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value); OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
// retval = mem_ap_read_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
return retval; return retval;
} }