interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

target/cortex_m: remove wrong xPSR.ICI/IT bits handling 

If a Cortex-M (not M0, M0+) target was stopped in the middle of
a conditional IT block or in the load/store multiple instruction,
cortex_m_debug_entry() used wrong xPSR bits to detect it and then
cleared 8 bits of the exception number from xPSR
- probably wrong bit mask again.

I believe clearing of the ICI/IT bits in cortex_m_debug_entry() has no
reason as Cortex-M does not use instruction injecting.

Remove the wrong code.

The change was originally a part of http://openocd.zylin.com/4862
It is now re-submitted as #4862 is not ready.

Change-Id: If91cd91d1b81b2684f7d5f10cf20452cde1a7f56
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5874
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Tomas Vanek 2020-10-22 12:50:24 +02:00 committed by Antonio Borneo
parent fc91936be7
commit f32ca2d25d
1 changed files with 0 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/target/cortex_m.c
View File

@ -527,12 +527,6 @@ static int cortex_m_debug_entry(struct target *target)
r = arm->cpsr; r = arm->cpsr;
xPSR = buf_get_u32(r->value, 0, 32); xPSR = buf_get_u32(r->value, 0, 32);
/* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
if (xPSR & 0xf00) {
r->dirty = r->valid;
cortex_m_store_core_reg_u32(target, ARMV7M_REGSEL_xPSR, xPSR & ~0xff);
}
/* Are we in an exception handler */ /* Are we in an exception handler */
if (xPSR & 0x1FF) { if (xPSR & 0x1FF) {
armv7m->exception_number = (xPSR & 0x1FF); armv7m->exception_number = (xPSR & 0x1FF);